Infineon Technologies Ag

Bernhard Dobler

Georg Georgakos

Alexander Nielsen

Erwin Ruderer

Walther Lutz

In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with the fins in the first direction above the substrate. The gate line extends in a second direction above the substrate, and partially wraps around the fins. The gate contact landing pad is positioned adjacent to or above the dummy fin and electrically coupled to the gate line. The gate contact element is electrically coupled to the gate contact landing pad and is positioned to the top surface thereof.

Contact structure for FinFET device

A layout structure is provided with a conducting line extending in a conducting line direction, the conducting line being arranged within a substrate area, a fill element being arranged within the substrate area at a predetermined distance from the conducting line, the fill element having a fill element axis extending perpendicularly to a side of the fill element in a fill element direction, an angle between the conducting line direction and the fill element direction being greater than 0&#xb0; and smaller than 90&#xb0;.

Layout structure having a fill element arranged at an angle to a conducting line

A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area. The method includes generating a next fill pattern on the next level fill area outside of a forbidden area of said next level fill area, modifying the first level forbidden area to extend at least over the electrical component and the first portion of the conductor, and removing any of the plurality of structures in the fill pattern that are within the modified first level forbidden area.

Method for generating fill and cheese structures

A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, at least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least on fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh.

Growing community of inventors

Erding, Germany

Bernhard Dobler