Vitesco Technologies Gmbh

Cpt Group Gmbh

Bernhard Bieg

Alfons Fisch

Andreas Wunderlich

Klaus-Dieter Schneider

Christoph Haggenmiller

Andrey Shadrin

A method assigns addresses from a master unit to a number of slave units. The slave units are connected to the master unit for the transmission of information. An address output of the master unit is connected to an address input of a first slave unit and the address output of an n-th slave unit is connected to the address input of an n+1-th slave unit. The slave units, when a first level is applied to their address input, set the level at their address output to the first level and change to the first, 'non-addressed' state, in the event of a transition of the level at their address input from the first level to a second level, change to the 'addressable' state, upon receiving an address from the master unit, check the received address for validity in the &#x201c;addressable&#x201d; state and, acknowledge the reception to the master unit.

Method for the assignment of addresses by a master unit to a number of slave units

A circuit arrangement includes a microcontroller having a first analog-to-digital converter whose input is connected to the output of a first multiplexer whose output is connected to a first comparison device for comparing reference voltages, and a first serial interface circuit connected to the first comparison device. A voltage generating circuit includes a second analog-to-digital converter whose input is connected to the output of a second multiplexer whose output is connected to a number of registers, which are connected to a safety value generator and store digital values together with a respective safety value, and a second serial interface circuit connected to the registers. The first and second serial interface circuits are connected to each other for communication of the microcontroller with the voltage generating circuit, the first interface circuit being connected to a second comparison device for comparing supply voltages and/or currents with desired voltages and/or desired currents.

Circuit arrangement comprising a microprocessor and a voltage generating circuit

An integrated circuit includes a reception port an address port, and a memory with a number of memory sections for storing activation information. The number of memory sections is equal to the number, encodable by the address port, of activatable integrated circuits that are operable over a common bus. A control unit is configured to compare the address encoded by the address port with an address received at the reception port. The control unit writes a defined bit pattern to the memory section associated with the address in the event of a positive comparison, and withholds transmission of a negative acknowledgement signal in the event of a negative comparison. The integrated circuit is configured to be activated by the defined bit pattern in the memory section that corresponds to the address defined at the address port, for communicating with a microprocessor connected to the integrated circuit via the common bus.

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Wuppertal, Germany

Bernhard Bieg