Motorola Corporation

M/a -com, Inc.

Bernhard A Ziegner

Hugh Robert Malone

Allen E Christ

Jean C Collinet

Michael L Matson

Dennis R Sprague

James A Bowen

Pramode Kandpal

A two-terminal field effect transistor device which is capable of operation as an oscillator including a field effect transistor connected in a two-terminal manner. The transistor has the usual drain source and gate electrodes and oscillating instability is provided by means of an inductance means of value so as to provide this circuit instability to enable circuit oscillations. The two-terminal arrangement is enabled by means of essentially interconnecting the gate and drain electrodes by way of said inductance means.

Field effect transistor device

Electrical coupling to the ground plane of an MIC is accomplished by forming a gap adjacent an edge of the ground plane and causing a virtual short to appear across the gap. A two part, one-half wavelength transmission line transformer is used to provide the virtual short. The transformer is defined by the conductive members surrounding the MIC and is open at the end corresponding to the gap and shorted at the other end. The impedances of the two parts of the transformer are chosen to maximize the bandwidth of the virtual short.

Noncontacting MIC ground plane coupling using a broadband virtual short

An apparatus and method is disclosed for allowing faster and higher fidelity signals to be transmitted from a PC board to an IC by maintaining a constant impedance from the PC board to the IC. A leadless chip connector is used with a ground plane mounted co-planar to the conductor. As the conductor and ground planes extend toward the IC they decrease in width and the distance between the conductor and ground plane varies to maintain a constant impedance.

LCC co-planar lead frame semiconductor IC package

A hybrid integrated circuit package and a method for fabricating the package. The package comprises a ceramic substrate having a blank metallization and feedthroughs screen printed thereon. A ceramic seal ring is joined to the substrate to form the side walls of the package. The substrate metallization is plated with nickel and gold and external leads are brazed to the ends of the feedthroughs. As such the package is suitable for use with a large number of different integrated circuits. The package can be adapted for use with a particular integrated circuit function by selectively patterning the blank substrate metallization. This is accomplished by laminating a preformed piece of dry film photoresist material to the package bottom. This piece of photoresist is then exposed through a photographic mask using a collimated light source.

Making hybrid IC with photoresist laminate

A semiconductor packaging configuration is described in which a heat sink is bonded to a semiconductor chip or die and a conductor is bonded to the die and a metalized ceramic insulating body for achieving optimum heat transfer. Additionally, electrical matching and/or reduction of parasitic elements is achieved by a low pass matching filter comprising the capacitance of the chip or die, the capacitance of the metalized ceramic body and the inductance of the electrical conductor. This provides a significant improvement in power handling capabilities of a semiconductor chip or die operating at elevated temperatures and gigahertz frequencies. The electrical conductor geometry and its bonds provide a reduction of the thermal resistance of the package and also provides the inductance which forms part of the low pass matching filter.

Growing community of inventors

Westford, MA, United States of America

Bernhard A Ziegner