Siemens Aktiengesellschaft

Bernd Zehner

Matthias Schoebinger

Fred Matthiesen

Ulrich Totzek

Reinhard Tielert

In DPCM coders, respective estimated values are subtracted from digitized picture element signals and the estimated errors are employed for signal transmission following quantization and coding. Each estimated error is quantized with a fictitious, positive operational sign in a first programmable logic arrangement and, parallel thereto, is quantized with a fictitious negative operational sign in a second programmable logic arrangement. Of these two quantizing results, the correct result is selected via a multiplexer controlled by the actual operational sign of the estimated error.

Arrangement for DPCM coding of television signals with fast signal

In a DPCM coder respective estimated values are subtracted from digitized picture element signals and estimated errors are used for signal transmission after quantization and coding. Each estimated value is derived from a reconstructed picture element signal formed in an adder. Separate, simultaneous subtractions of the signal taken at the output of the adder, as well as of the positive and negative adder limit values, from the respective picture element signal at the input thereby occur, whereby an overflow recognition device and a multiplexer provide that only the difference from the three differences formed up to this point are taken into consideration for quantization on the basis of the actual addition result, including no overflow, positive overflow and negative overflow.

Arrangement for past DPCM coding of video signals according to a 2-D or

A circuit arrangement comprises a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions and contains three-transistor cells having overlapping write/read cycles as storage elements. A row selector is clocked controlled by the input clock of the incoming image signals and is continuously steppable and resettable at any time. The row selector comprises, respectively, two phase offset signal outputs per selection step which respectively drive a write word line and a read word line and which are provided per row of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of the column. A storage amplifier which is disconnectible from the read bit line is provided per column and has an input connected to the read bit line of the assigned column and an output connected to the bit write line of the following column and serves as a data output. A reset input is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time to be set between the undelayed data output and a first, delayed data output. A plurality of such memory-shaped memory arrangements is provided in accordance with the word width of the image data the row selector being provided in common for such plurality, whereby a respective memory block accepts one bit of the image data word and offers the same as the respective corresponding bit of a plurality of differently time delayed output data words. An arithmetic unit combines the data outputs, by adding or, respectively, subtracting, in an arrangement of cascaded logic elements in order to achieve the required filter function.

Circuit arrangement comprising a matrix-shaped memory arrangement for

An improved memory cell for use in an associative memory has a RAM cell having two output terminals respectively connected to a bit line and a complementary bit line through transistors having respective control electrodes connected to a word line. The outputs of the RAM cell are also cross-connected to the control electrodes of further transistors respectively connected to the bit lines and having a common terminal connected to the controlled electrode of a transistor which determines the state of a hit line. When the word line is activated, information occurring on the bit line is written into the RAM cell. If the word line is non-activated, information supplied by the bit line is compared to information currently stored in the RAM cell and the result of the comparison is utilized to determine the state of the hit line.

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Munich, Germany

Bernd Zehner