Infineon Technologies Ag

Infineon Technologies Austria Ag

Bernd Roemer

Ralf Otremba

Edward Fuergut

Josef Hoeglauer

Klaus Schiess

Xaver Schloegel

Juergen Schredl

Jens G Pohl

Manfred Engelhardt

Erich Griebl

Holger Woerner

Christian Stuempfl

Fabio Brucchi

Hannes Eder

Bernhard Zuhr

Bernhard Schaetzler

Herman Vilsmeier

A method of producing a semiconductor device is provided. The method includes: providing a semiconductor wafer, the wafer including an upper layer of a semiconductor material, an inner etch stop layer and a lower layer; forming a plurality of functional areas in the upper layer; performing a selective first etch process on the upper layer so as to separate the plurality of functional areas from each other by trenches etched through the upper layer, the first etch process being substantially stopped by the inner etch stop layer; and removing the lower layer by a second etch process, the second etch process being substantially stopped by the inner etch stop layer.

Method of producing a semiconductor device and a semiconductor device

A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Method for manufacturing a chip arrangement

A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Chip arrangements and methods for manufacturing a chip arrangement

A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

Chip package and a method for manufacturing a chip package

An electronic semiconductor module component with a semiconductor stack includes semiconductor components arranged in a vertically stacked relationship. A basic semiconductor component includes a lower interposing unit, on which lower external contact pads are arranged. The basic semiconductor component further includes an upper interposing unit, on which upper external contact pads are arranged. The two interposing units are electrically connected to one another via bonding connections disposed at their edge areas. The basic semiconductor component is a compact component on which different, customer-specific semiconductor components can be stacked.

Semiconductor module with a semiconductor stack, and methods for its production

Growing community of inventors

Bernhardswald, Germany

Bernd Roemer