Infineon Technologies Ag

Siemens Aktiengesellschaft

Continental Automotive Gmbh

Siemens Aktiengesell Schaft

Seimens Aktiengesellschaft

Kargl, Anton

Bernd Meyer

Wieland Fischer

Michael Braun

Anton Kargl

Steffen Sonnekalb

Gerd Dirscherl

Markus Dichtl

Erwin Hess

Jan Otterstedt

Berndt Gammel

Rainer Goettfert

Christian Peters

Cheow Guan Lim

Stephan Schaecher

Jean Georgiades

Robin Boch

Thomas Poeppelmann

Hermann Seuschek

Stefan Pyka

Marcus Schafheutle

Thomas Kuenemund

Jean-Pierre Seifert

Gunther Fenzl

Franz Klug

Joel Hatsch

Thomas Grill

Horst Plankenhorn

Florian Mendel

Dietmar Zaig

Rainer Göttfert

Benedikt Driessen

David Von Oheimb

Achim Schmidt

Detlef Böhler

Peter Soehne

A device for processing bit strings of a program flow including a data memory and an interface that is designed to output a second bit string, and a bit string manipulator that is designed to analyze the first bit string at a predetermined bit string section for information that indicates a target state of the program flow, and to manipulate the first bit string in the bit string section to obtain the second bit string.

Device and methods for processing bit strings

A method for providing challenges to a device comprising (i) compiling a first challenge based on a first random value and a parameter; (ii) compiling a second challenge based on a second random value, the parameter and based on the first challenge or any intermediate result thereof; and (iii) providing the first challenge and the second challenge to the device.

Providing a challenge to a device

A method is proposed for copying a source array into a target array, wherein both the source array and the target array have at least two elements, wherein each element has a value, in which the elements of the source array are copied into the target array in the sequence of a random permutation, wherein, after a step of copying an element of the source array into the target array, the source array, the target array or the source array and the target array are rotated. A device is also indicated accordingly.

Protection against side-channel attacks

It is proposed to divide data read from a memory into groups and to perform a syndrome calculation iteratively based on each of the individual groups. The syndromes may be calculated by means of random access to the individual groups.

Processing of data read from a memory

An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.

Integrated circuit

According to one embodiment, an execution unit is described, which includes a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations.

Execution unit for calculations with masked data

A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.

Address-coded access towards memory

A chip includes a processing device to perform cryptographic operations by secret data; a memory to store a first plurality of information portions that correspond to a first breakdown of the data and from which the secret data are reconstructible by combination of the first plurality of information portions; a random number generator to provide random values; and a conversion device to ascertain second breakdowns of the data into a second plurality of information portions, from which the secret data are reconstructible and to control the memory for an ascertained second breakdown to store the present second plurality of information portions. The conversion device is further configured to ascertain the second breakdowns based on the random values and/or to determine the interval of time between the ascertaining and storing of a second breakdown and the ascertaining and storing of the subsequent second breakdown based on the random values.

Chip and method for securely storing secret data

One embodiment describes a method for permuting data elements, comprising receiving a sequence of data elements, and carrying out a plurality of interchange operations each comprising randomly selecting a data element from the data elements in the sequence, interchanging the data element with another data element at a deterministically predefined position in the sequence of data elements, and applying a predefined permutation to the deterministically predefined position or to the sequence of data elements.

Method for permuting data elements and permuting apparatus

A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

Memory circuit and method of operating a memory circuit

An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.

Integrated circuit and method for processing an encoded message word

A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Data encryption and verification between master and slave

A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.

Verifying memory access

A memory arrangement having a memory cell array, wherein each column is associated with a bit line and each row is associated with a word line, wherein the columns have first columns of memory cells that store useful data, and columns of memory cells of a second column type that store prescribed verification data, wherein during a read access operation the memory cells of at least the columns of memory cells of the second column type set the associated bit line to a value that corresponds to a logic combination of the values stored by the memory cells of the column of the second column type that belong to rows of memory cells addressed during the read access operation, and a detection circuit that is configured to, during a read access operation, detect whether a bit line associated with a column of memory cells of the second column type is set to a value that corresponds to the logic combination of values stored by memory cells of the column of the second column type of memory cells and whose values belong to different rows of memory cells.

Memory arrangement and detection circuit for data protection

Memory circuit including overlay memory cells and method of operating thereof

Growing community of inventors

Munich, Germany

Bernd Meyer