International Business Machines Corporation

Bernd Karl-Heinz Appelt

Donald Seton Farquhar

Michael Joseph Klodowski

Ross William Keesler

Andrew Michael Seman

James Russell Bupp

Gary Lee Schild

Voya Rista Markovich

John M Lauffer

Konstantinos I Papathomas

Robert Maynard Japp

Anilkumar Chinuprasad Bhatt

William E Wilson

William John Rudik

Christina Marie Boyko

Stephen Joseph Fuerniss

James W Fuller, Jr

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

Manufacturing methods for printed circuit boards

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.

A printed circuit board comprising a plurality of conductive bumps having substantially coplanar upper surfaces is provided. The circuit board is formed by providing: a substantially planar metallic layer having a first thickness on at least one surface of the dielectric; applying a first photoresist on the metal layer; imaging the first photoresist to define a pattern of conductive bumps; etching the exposed portions of the metal layer to a second thickness to form the conductive bumps; removing the first photoresist; applying a second photoresist to the metal layer; imaging the second photoresist to define a pattern of circuitry; etching the exposed portions of the metal layer to provide the electrical circuitry; and removing the second photoresist. The present invention also provides a method for preparing printed circuit boards wherein two conductive layers that are disposed on opposing sides of a dielectric layer are inter-connected by at least one of the substantially coplanar conductive bumps. The method comprises the additional steps of depositing a second dielectric layer on the substantially coplanar conductive bumps and circuitry; exposing the upper surface of at least one of the conductive bumps; and depositing a second metal layer on the second dielectric layer and the exposed upper surface of the conductive bump. The present invention is also related to a method for preparing a reinforced panel. The method comprises the steps of: applying a metal layer having a first height on at least one surface of a dielectric substrate; applying a first photoresist to the metal layer, imaging the photoresist to provide at least one section of remaining photoresist defining an opening therein and at least one exposed region of the metal layer; etching the exposed region of the metal layer to a second height; and removing the remaining photoresist to provide a multi-layered structure comprising a dielectric layer and a metal layer comprising at least one region having a second height and at least one region having a first height.

Printed circuit board with continuous connective bumps

A method for filling a hole in a printed wiring board (PWB) and the resultant PWB. During an intermediate stage in fabrication, a PWB comprises a lamination of dielectric sheets with metalizations on various layers and a plated through hole (PTH). A photoimageable material is formed on a surface of the laminate and covers the PTH. The photoimageable material in a region covering the PTH is partially cured by exposure to light. The remainder of the photoimageable material is developed away. Then, the partially cured photoimageable material in the region of the PTH is pressed into the PTH to form a plug. By application of heat during or after the forcing step, the plug is further cured to a hard condition. For some applications, the plug is mechanically abraded to be flush with one or both surfaces of the laminate. The plug can serve as a solder mask or permit another layer of low viscosity photoimageable material to be formed over the laminate such that the hole, now plugged, will not interfere with the formation of such additional layer.

Method for filling holes in printed wiring boards

A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

Electronic device packages having glass free non conductive layers

An integrated circuit chip package with an integrated chip carrier having differing coefficients of thermal expansion (CTE) in the x-y plane. The chip carrier is comprised of two main regions. The first is a core region having a CTE approximately equal to that of the semiconductor chip CTE. This core region also has approximately the same dimensions in the x-y plane as the semiconductor chip. The chip is mounted just above this core region. The second region is a peripheral region which surrounds the core region in the x-y plane. This second region has a CTE approximately equal to that of the printed circuit board CTE. During thermal cycling, the materials expand and contract. The core region expands at nearly the same rate as the chip and the area outside the chip footprint, the peripheral region, expands at a rate similar to that of the printed circuit board. This characteristic prevents thermal stress-induced fatigue on the package components and solder joints.

Growing community of inventors

Apalachin, NY, United States of America

Bernd Karl-Heinz Appelt