Globalfoundries Inc.

Qimonda Ag

Infineon Technologies Ag

Bernd Hintze

Frank Koschinsky

Henry Bernhardt

Frank Bernhardt

Xunyuan Zhang

Peter Baars

Stephan Kudelka

Wolfgang Roesner

Hans-Peter Moll

Gerhard Enders

Martin Popp

Klaus Muemmler

Stefan Jakschik

Werner Graf

Peter Lahnor

Tibor Bolom

Lars Heineck

Arnd Scholz

Dirk Utess

Andrei Josiek

Oliver M Witnik

Gouri Sankar Kar

Heiko Weber

Kun Ho Ahn

Jonas Sundqvist

A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.

Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Methods for fabricating integrated circuits including barrier layers for interconnect structures

Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

Methods of forming metal nitride materials

A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.

Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process

A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

Method for detecting defects in a diffusion barrier layer

One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Interconnect structure for semiconductor devices

A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer

In a method for producing a conductive layer a substrate is provided. On the substrate, a layer includes at least two different metal nitrides. In one embodiment, on a surface of the substrate a first metal nitride layer is deposited, followed by a second metal nitride layer formed thereon. A third metal layer is then deposited on a surface of the second metal nitride layer.

Method of producing a conductive layer including two metal nitrides

Growing community of inventors

Langebrueck, Germany

Bernd Hintze