Ihp Gmbh-Innovations for High Performance Microelectronics/institut Fur Innovative Mikroelektronik

Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh

Ihp Gmbh-Innovations for High Performance Microelectronics/leibniz-Institut Fur Innovative Mikroelektronik

Nokia Corporation

Ihp Gmbh - Innovations for High Performance Microelectronics

Ihp Gmbh - Innovations for High Performance

Ihp Gmbh - Innovations for High Performance Microelectronics/instut Fur Innovative Mikroelektronik

Institut Fuer Halbleiterphysik Franfurt (Oder) Gmbh

Ihp Gmbh—innovations for High Perforamce Microelectronics/leibniz-Institut Fur Innovative Mikroelektronik

Ihp-gmbh—innovations for High Performance Microelectronics/leibniz-Institut Fur Innovativ Mikroelektronik

Ihp Gmbh—innovations for High Performance Microelectronics / Leibniz-Instut Für Innovative Mikroelektronik

Ihp Gmbh - Innovations for High Performance Microelectronic / Institut Fur Innovative Mikroelektronik

Ihp Gmbh-Innovations for High Performance Microelectronics/institute for Innovative Mikroele

Ihp Gmbh - Leibniz Institute for High Performance Microelectronics/ Leibniz-Institut Für Innovative Mikroelektronik

Bernd Heinemann

Dieter Knoll

Karl-Ernst Ehwald

Bernd Tillack

Holger Rücker

Gunther Lippert

Steffen Marschmeyer

Alexander Fox

Dirk Wolansky

Hans-J&ouml;rg Osten

Wolfgang Winkler

Jürgen Drews

Steffen Marschmayer

Hans-Jörg Osten

Yuji Yamamoto

Katrin Blum

Peter Schley

Juergen Drews

Eberhard Bugiel

A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.

Method for fabricating a bipolar transistor having self-aligned emitter contact

A semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, said portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.

Bipolar transistor having self-adjusted emitter contact

A method of depositing polycrystalline silicon exclusively on monocrystalline first silicon surface portions of a substrate surface which besides the first surface portions additionally has insulator surface portions, comprising the steps of depositing boron on the first silicon surface portions in an amount which in relation to the first silicon surface portions respectively corresponds to more than a monolayer of boron, and depositing silicon on the first silicon surface portions treated in that way.

Selective growth of polycrystalline silicon-containing semiconductor material on a silicon-containing semiconductor surface

A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.

Complementary bipolar semiconductor device

A vertical heterobipolar transistor comprising a substrate of semiconductor material of a first conductivity type and an insulation region provided therein, a first semiconductor electrode arranged in an opening of the insulation region and comprising monocrystalline semiconductor material of a second conductivity type, which is either in the form of a collector or an emitter, and which has a first heightwise portion and an adjoining second heightwise portion which is further away from the substrate interior in a heightwise direction, wherein only the first heightwise portion is enclosed by the insulation region in lateral directions perpendicular to the heightwise direction, a second semiconductor electrode of semiconductor material of the second conductivity type, which is in the form of the other type of semiconductor electrode, a base of monocrystalline semiconductor material of the first conductivity type, and a base connection region having a monocrystalline portion which in a lateral direction laterally surrounds the second heightwise portion, which is further towards the substrate interior as viewed from the base, of the first semiconductor electrode, and which rests with its underside directly on the insulation region.

Vertical bipolar transistor

A bipolar transistor has a base with an epitaxial base layer and a raised base connection region which in a lateral direction in parallel relationship with the substrate surface encloses the emitter which is surrounded by a spacer of insulating material. The epitaxial base layer is raised in a heightwise direction perpendicularly to the substrate surface. An emitter of a T-shaped cross-sectional profile is separated laterally from the outer base portion by a spacer of insulating material. Its vertical bar of the T-shape adjoins with its lower end the inner base portion. The lateral extent of the spacer increases from its interface with respect to the base layer with increasing height above the base layer, wherein a first interface formed by the emitter and the spacer meets a second interface formed by the emitter and the inner base portion at a first angle which is either a right angle or an obtuse angle, and a third interface formed by the spacer and the outer base portion meets the second interface at a second obtuse angle which is larger than the first angle.

Bipolar transistor with raised base connection region and process for the production thereof

The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate () with one or more buried high-carbon Si layers () under an epitaxial layer and with the Si cap layer (), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.

Layers in substrate wafers

The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.

Semiconductor device and method for production thereof

The invention concerns a bipolar transistor with an epitaxially grown base and a self-positioned emitter, whereby the base is formed from a first substantially monocrystalline epitaxial region () which is arranged in parallel relationship to the surface of the semiconductor substrate () and a second substantially polycrystalline and highly doped region () of the same conductivity type which is arranged in perpendicular relationship to the substrate surface and encloses the first region at all sides and that said second region, at least at one side but preferably at all four sides, is conductingly connected to a third, preferably highly doped or metallically conducting, high temperature-resistant polycrystalline layer () which is arranged in parallel relationship to the surface of the semiconductor substrate and forms or includes the outer base contact to a metallic conductor track system.

BiCMOS structure, method for producing the same and bipolar transistor for a BiCMOS structure

A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low 'on' resistance, characterised in that disposed in the region of the drift space () which is between the highly doped drain region () and the control gate () and above the low doped drain region LDDR () of the transistor is a doping zone () which is shallow in comparison with the penetration depth of the source/drain region (), of inverted conductivity type to the LDDR () (hereinafter referred to as the inversion zone) which has a surface area-related nett doping which is lower than the nett doping of the LDDR () and does not exceed a nett doping of 8E12 At/cm2.

DMOS transistor

The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.

Method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip

A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, the concentration profile of germanium in the base layer has a general shape of a triangle or trapezoid.

Silicon germanium hetero bipolar transistor having a germanium concentration profile in the base layer

A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-&#x3bc;m production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.

Cmos-compatible lateral dmos transistor and method for producing such a transistor

A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.

Silicon-germanium hetero bipolar transistor with T-shaped implantation layer between emitter and emitter contact area

A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, carbon is incorporated in the base layer and in the collector layer and/or emitter layer.

Growing community of inventors

Frankfurt-am-Main, Germany

Bernd Heinemann