Daimler Chrysler Ag

Robert Boschgmbh

Bayerische Motoren Werke Aktiengesellschaft

Gm Global Technolgoy Operations, Inc.

Motorola Corporation

Freescale Semiconductor,inc.

Nxp B.v.

Koninklijke Philips Corporation N.v.

Decomsys—dependable Computer Systems, Hardware Und Software Entwicklung Gmbh

Bernd Hedenetz

Anton Schedl

Thomas M Forest

Peter Fuhrmann

Christopher Temple

Martin Peller

Mathias Rausch

Josef Berwanger

Bernd Müller

Arnold W Millsap

Ralf Belschner

Thomas Führer

Florian Hartwich

Robert Hugel

Christian Ebner

Florian Bogenberger

Manfred Bruno Zinke

Bernd Elend

Harald Eisele

Jörn Ungermann

Harald Weiler

Peter Lohrmann

Thomas Wuerz

Patrick Willem Heuts

Matthias Kühlewein

Gregor Pokorny

Ing Ralf Belschner

The invention refers to a method for monitoring a communication media access schedule of a communication controller () of a communication system () by means of a bus guardian (). The communication system () comprises a communication media () and nodes () connected to the communication media (). Each node () comprises a communication controller () and a bus guardian () assigned to the communication controller (). Messages are transmitted among the nodes () across the communication media () based on a cyclic time triggered communication media access scheme. In order to provide a mechanism which allows the bus guardian () to monitor the communication media access scheme of the communication controller () even during startup of the communication it is suggested, that the bus guardian () has a priori knowledge about possible deviations from the communication media access schedule during startup of the communication and that the bus guardian () during startup makes use of the a priori knowledge to distinguish between an allowed deviation and a forbidden deviation caused by a failure of the communication controller ().

Method for monitoring a communication media access schedule of a communication controller of a communication system

The invention concerns a network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network and are designed to adapt their local communication time schedule to the communication time schedule of at least one other network mode, prior to being integrated as active network nodes. A network node to be integrated checks the activity of other network nodes and if no activity is identified, sends out positional messages for other network nodes, said message being fixed by predetermination in its communication time schedule. If a network node cannot be integrated as a reference node, it can only be integrated as an active node if it adapts its local communication time schedule to that of the reference node after receiving positional messages and if a check as to whether its own communication time schedule agrees with the communication time schedules of at least some of the active network nodes proves positive.

Network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network

A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.

Method and bit stream decoding unit using majority voting

The present invention provides an improved clock synchronization algorithm for a distributed system intended for real time applications by performing at the same time an off-set correction and a clock read correction at each node of the distributed system. Expensive oscillators can be avoided and synchronization can be established faster and with higher precision.

Clock synchronization in a distributed system

A central node for a data bus system includes a bus monitor unit with receiver means for registering signals on the data bus, and evaluation means which detect incorrect communication on the data bus and at least temporarily block communication by the user that causes the incorrect communication or compensate the incorrect communication of a user which is triggered by the interference influences. The bus monitor unit includes timing means which are triggered according to time patterns for the transmission of each user of the data bus, in order to detect an incorrect communication of a user if the latter transmits outside the time provided for it. The bus monitor unit is integrated into the central bus node and a plurality of bus branches of different users are combined at the central node so that the bus monitor unit can check a plurality of users for incorrect communication. In order to increase reliability, in addition to the bus monitor unit, a diagnostic unit is integrated into the central node. The latter monitors the bus monitor unit in terms of regular retriggering in response to the time patterns, so that the bus monitor unit can be deactivated in the absence of retriggering.

Bus monitor unit

A vehicle steering and braking system includes a distributed control loop in which a state-determining device for generating signals that describe current vehicle operation, an arithmetic unit for generating set point signals and a regulator unit for generating actuator signals are connected to one another by a data bus. The signals of the devices and units, which are transmitted via the data bus, are combined in cycles, one complete set of information being capable of being transmitted via the data bus in each cycle. Within a single cycle the signals of the respective units and devices are generated and transmitted via the data bus in the sequence: arithmetic unit&mdash;state-determining device&mdash;regulator unit. Each of the components comprising the arithmetic unit&mdash;state-determining device and regulator unit, however, can form the starting point of the sequence without changing the sequence itself.

Steering and braking system for a motor vehicle

Growing community of inventors

Denkendorf, Germany

Bernd Hedenetz