Seagate Technology Incorporated

Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Smart Storage Systems, Inc.

University of Minnesota

Sandisk Enterprise IP LLC

Bernardo Rub

Ara Patapoutian

Bruce Douglas Buch

James Fitzpatrick

Kinhing Paul Tsang

Robert W Ellis

James M Higgins

Hamid R Shafiee

Richard David Barndt

Mark Joseph Dancho

Mostafa El Gamal

Ryan R Jones

Arvind Sridharan

Robert D Cronch

Peter Igorevich Vasiliev

Kenneth R Burns

Timothy Richard Feldman

Jingfeng Liu

Jaekyun Moon

James Joseph Touchton

Vadim B Minuhin

Prafulla Bollampalli Reddy

Jimmie Ray Shaver

Clifton James Williamson

Bengt Anders Ulriksson

Hui Su

Ke Du

Sheunghee Park

Robert E Kost

Gary W Reininga

Barret J Brickner

Mary Elizabeth Dunn

John Scaramuzzo

Peihui Zheng

Srinivas Maddali

Wuping Chen

Kavi Alptekin

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

Multi-state programming for memory devices

A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices.

Data management in a storage system

Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.

Data storage system with dynamic erase block grouping mechanism and method of operation thereof

A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate.

Storage control system with power-off time estimation mechanism and method of operation thereof

Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Opportunistic decoding in memory systems

A method of operation of a non-volatile memory system includes: generating a test stimulus for a page in a memory array; measuring a test response from the page in the memory array based on the test stimulus; calculating a measured effective life of the page from the test response; and determining a use plan according to the measured effective life for accessing the page.

Non-volatile memory management system with load leveling and method of operation thereof

A method of operation of a storage control system includes: partitioning logical addresses into a number of subdrives, the logical addresses associated with a memory device; and monitoring a data write measure of one of the subdrives.

Storage control system with write amplification control mechanism and method of operation thereof

A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.

Iterating inner and outer codes for data recovery

Various approaches that reduce the width variability of storage media data tracks are described. First and second data tracks are written so that the second track overlaps the first track. After writing the second track data to the second track, an effective width of the first track is determined. The effective width of the first track is the portion of the first track that is not overlapped by the second track. One or more additional write operations to the recording medium are performed to compensate for the effective width of the first track being less than a threshold. The additional write operations may include one or more of rewriting the first track data to a third track on the storage medium and writing additional redundancy information to supplement the coding of the first track data.

Reducing errors resulting from width variability of storage media write tracks

An apparatus may comprise a memory including a first area of total usable storage capacity of the memory reported to a host device, a second area occupied by error correction code (ECC) appended to data stored in the first area, and a third area of usable data storage capacity not reported to the host device. The apparatus may further comprise a controller configured to balance sizes of the second area and third area to maintain a size of the first area as the length of ECC of data stored in the first area increases. The controller may be further configured to exchange data having an ECC of a controllable length with the memory based on a data storage location, and adjust the controllable length of the ECC based on an error history of the data storage location.

Adjustable memory allocation based on error correction

The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.

Methods and devices to reduce outer code failure rate variability

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Sudbury, MA, United States of America

Bernardo Rub