Sun Microsystems, Inc.

Oracle America, Inc.

Bernard Tourancheau

Cedric Koch-Hofer

Xavier-Francois Vigouroux

Ivan E Sutherland

Robert J Drost

Ronald Ho

Hans Eberle

Nils Gura

Danny Cohen

Jo C Ebergen

Nicolas Fugier

Henri Gouraud

A system includes a plurality of integrated circuits for propagating data between at least one central processing unit and another component of the system. The plurality of integrated circuits are configured for proximity I/O communication. The plurality of integrated circuits is configured such that data propagation through the plurality of integrated circuits is unaffected by a rotation of at least one of the plurality of integrated circuits by 90 degrees.

Network chip design for grid communication

An electronic system in which integrated circuits employing cornered I/O are arranged in a framework including an optional path manager and at least one updateable routing table. Packet routing options are described with solutions being provided to minimize transmission latency and pathway alternatives.

Optimal communication path routing in a system employing interconnected integrated circuit technology

A system, including at least one central processing unit, at least one memory unit, and a plurality of integrated circuits that form a switching fabric configured to propagate data packets between the at least one central processing unit and the at least one memory unit, wherein the switching fabric is constructed using at least two directed acyclic graph (DAG) networks.

Implementation of a graph property in a switching fabric for fast networking

One embodiment of the present invention provides a system for routing data between integrated circuit devices. This system couples together an n-dimensional grid of integrated circuit devices using multiple independent communication networks, wherein each of the communication networks only moves data in two orthogonal directions (e.g., North and East, North and West, South and East, or South and West). The system also includes a routing mechanism that routes data across these communication networks, as well as, into, out of, and through integrated circuits within the n-dimensional grid of integrated circuits. Note that the process of routing a signal across a given network is greatly simplified because it is not possible to create a cycle that causes a deadlock within a given network.

Method and apparatus for routing data across an n-dimensional grid network

One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Method and apparatus for performing error-detection and error-correction

An arbiter is used so multiple users can use shared resources. The arbiter allocates at least one of the resources speculatively to one of the users for use during a particular access interval in the absence of a request for the resource from the user. The arbiter can also allocate one or more of the resources for use during the particular access interval in response to requests received by the arbiter for the resource(s). That is, a particular access interval may include both speculative and non-speculative allocation of resources by the arbiter.

Method and apparatus for speculative arbitration

A system and method for determining a carrier layout using cornered chip-to-chip input/output is presented. Each of a plurality of individual integrated circuit carriers communicatively interfaceable through cornered input/output ports is oriented at a uniform rotation relative to an edge of a carrier layout. Each carrier defines a set of rectilinear edges. Each carrier is placed juxtaposed at an open corner to at least one other carrier within a rectilinear lattice topologically arranged in the carrier layout to substantially minimize Hamming distances between each of the carriers.

System and method for determining a carrier layout using cornered chip-to-chip input/output

One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.

Growing community of inventors

Miribel, France

Bernard Tourancheau