Bell Telephone Laboratories

At&t Bell Laboratories

Bernard T Murphy

William Joshua Evans

Wesley Norman Grant

Adrian R Hartman

Peter W Shackle

Terence J Riley

Charles M Lee

James C North

Roger Edwards

An integrated circuit chip in which clock pulses are distributed to a plurality of circuits includes a pattern of trimmable elements such as capacitors or transistors. The capacitors or transistors are trimmed during manufacture in order, for example, to adjust clock skew.

Trimmable loading elements to control clock skew

A high voltage solid-state switch, which provides bidirectional blocking, consists of a first p- type semiconductor body on an n type semiconductor substrate. A p+ type anode region and an n+ type cathode region exist in portions of the semiconductor body. A second p type region of higher impurity concentration than the semiconductor body surrounds the cathode region. The anode region and second p type region are separated from each other by a portion of the semiconductor body. The semiconductor substrate, which acts as a gate, has an electrode connected thereto. Separate electrodes are connected to the anode and cathode regions.

High voltage junction solid-state switch

Disclosed is a method of isolating portions of integrated circuits which permits closely packed structures. A semiconductor wafer is provided with a substrate of one conductivity type, a first layer of opposite conductivity type and high impurity concentration formed thereon, and a second layer of either conductivity type but lower concentration formed over the first layer. The major surfaces of the semiconductor layers are parallel to the (110) plane. Narrow grooves with sidewalls in the (111) plane are etched into the first layer. A shallow diffusion of impurities of the same conductivity type as the first layer is performed in the sidewalls and bottom of the grooves which permits the first layer to be contacted from the surface of the second layer. The groove is then etched further until it extends into the underlying substrate. Impurities of the same conductivity type as the substrate are diffused into the bottom and sidewalls of the grooves. The concentration of these impurities is chosen so that a chanstop region is formed in the substrate without appreciably affecting electrical conductivity between the first layer and the regions formed by the previous diffusion.

Isolation of integrated circuits utilizing selective etching and

An integrated injection logic circuit cell structure and its fabrication are simplified. A pattern of oxide isolation regions is used to define, at least partially, the introduction of two types of impurities in such a way as to reduce the number of masking steps. Certain of these oxide regions do not penetrate through the conventional epitaxial layer, leaving a lateral buried path to serve as the base of a lateral injection transistor. A pattern of polycrystalline silicon containing impurities is used both as a diffusion source and an interconnection.

Integrated injection logic using oxide isolation

A method of making an oxide isolated integrated circuit structure is simplified by forming a first level metallization pattern without the conventional underlying insulating layer and without the need for restricting the size of the metallization to the size of the semiconductor regions to be contacted. Portions of the first level metallization pattern can extend on the oxide isolation region to contact two otherwise isolated semiconductor zones. Additionally, subsequent to the formation of the oxide isolation regions and the first level metallization, an intermediate dielectric masking pattern is formed so the combination of the first level metallization, the oxide isolation regions and the masking pattern defines zones for the introduction of impurities. Further, the masking pattern alone is used to provide contact holes for a subsequently formed second level metallization pattern.

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Summit, NJ, United States of America

Bernard T Murphy