Bitmicro Networks, Inc.

Analog Devices International Unlimited Company

Bernard Sherwin Leung Chiw

Ricardo H Bruce

Margaret Anne Nadonga Somera

Shaun Bradley

Rey H Bruce

Andreas Callanan

Lawrence Moldez Salazar

Federico Zalzos Sambilay, Jr

Pat Crowe

Thomas J Meany

A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Error correction code validation

In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

Multi-level message passing descriptor

In an embodiment of the invention, a method which speeds up the transfer of data and increases the data throughput in an IO network comprised of Host Bus Adapters (HBAs)/IO bridges-switches, IO devices, and hosts is described. In the embodiment of the present invention, HBAs and IO bridges-switches utilize a multi-level cache composed of volatile memories (such as SRAM, SDRAM, etc.) and solid-state memories (such as flash, MRAM, etc.). These memories are used to cache the most recently accessed IO data by an active host or by another HBA/IO bridge-switch. Cache content can be from the local IO devices (the ones connected directly to the HBA/IO bridge-switch), from remote IO devices (the ones connected to different HBA/IO bridges/switches), or from both (a portion from local IO devices and another portion from remote IO devices). The combination of these caches from different HBAs/IO bridges-switches creates the cache for all IO devices in the entire network. Multiple copies of the same IO cache are possible depending on the transactions with the hosts.

IOC to IOC distributed caching architecture

In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps&#x2014;data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.

Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer

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Quezon, Philippines

Bernard Sherwin Leung Chiw