Stmicroelectronics Gmbh

Stmicroelectronics S.a.

Hitachi, Ltd.

St-ericsson Sa

Bernard Ramanadin

David Alan Edwards

Anthony Willis Rich

Andrew Michael Jones

John A Carey

Atsushi Hasegawa

Stephen James Wright

Shinichi Yoshioka

Takanobu Naruse

Margaret Rose Gearty

Vijaya Pratap Adusumilli

Robert (Yanxim) Chen

Gabriel Duffy

Tedder Meng

Wei Tao Wang

A system comprises a central processing unit (), an interconnection bus (), and a plurality of functional modules (-) corresponding to distinct power domains and able to communicate with each other and/or with the central processing unit via the bus. At least one of the power domains, and is configured to be substituted for a slave functional module () of the power domain when the power to the power domain is turned off by the central processing unit. It signals an error in response to any request of a transaction that is in progress between the slave functional module and a master functional module at the moment the power is turned off.

Power management system utilizing a transaction terminator

An output buffer register includes a first input flip-flop register receiving a given number N of input signals, a latching register, a selection register, and an output multiplexer delivering N output signals. Only one data input of the enable register receives an enable signal. In this way, the propagation time at the input of the buffer register is reduced.

Output buffer register, electronic circuit and method for delivering signals using same

An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Apparatus and method for shadowing processor information

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG-or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

System and method for communicating with an integrated circuit

A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface

DMA handshake protocol

A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

An integrated circuit which has a packet router to which a plurality of functional modules are connected by respective ports is described. One of the ports acts as a socket port for an expansion socket. The expansion socket provides a plurality of additional expansion ports to which additional functional modules can optionally be connected. All the ports connected to the packet router, including the expansion socket port, preferably lie in a common address space for the integrated circuit.

Integrated circuit with additional ports

In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.

Circuit for storing information

A substitution circuit for elementary flip-flop circuits is provided to enable the automatic transposition of a flip-flop circuit whose clock signal comes from a combinational logic circuit. To do this, an over-sampled internal clock signal is used along with a synchronous pulse generator to validate the data.

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Palo Alto, CA, United States of America

Bernard Ramanadin