Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics S.a.

Bernard Previtali

Maud Vinet

Thierry Poiroux

Fabrice Nemouchi

Sylvain Barraud

Jean-Pierre Colinge

Patrice Gergaud

Claire Fenouillet-Beranger

Simon Deleonibus

Jean-Charles Barbe

Olivier Rozeau

Pascal Besson

Christian Arvet

Christophe Licitra

Christian Vizioz

Gilles Fanget

A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.

Architecture with stacked N and P transistors with a channel structure formed of nanowires

Implementation of a device with stacked transistors comprising:

Architecture of N and P transistors superposed with canal structure formed of nanowires

A SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.

Method for fabricating an improved field effect device

A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.

Manufacturing of self aligned interconnection elements for 3D integrated circuits

A method for making a three-dimensional integrated electronic circuit is provided, including making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that it is disposed between the first and second dielectric layers, and a second semiconductor layer disposed on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the first electronic component to the first electrically conductive portion.

Method for making a three dimensional integrated electronic circuit

A SOI substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which faces the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a covering layer. The substrate is eliminated to access the source/drain regions. A second covering layer is deposited and access vias are formed to access the source/drain regions and gate electrode.

Fabrication method of an improved field effect device

A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.

Manufacturing method for a device with transistors strained by silicidation of source and drain zones

Method of producing an integrated electronic circuit comprising at least the steps of:

Method of producing a three-dimensional integrated circuit

A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Method of producing a device with transistors strained by means of an external layer

A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.

Method for making a transistor with metallic source and drain

A method for producing a transistor with metallic source and drain including the steps of:

Method for producing a transistor with metallic source and drain

A method for manufacturing at least one structure for a double grid field effect transistor, including: forming, on an isolating face of a first substrate, a stack comprising successively at least one layer of rear grid material, a layer of rear grid isolator, one semi-conducting zone for each structure to be manufactured, an electrically insulating layer of a front grid, at least one layer of front grid material and a masking element for each structure to be manufactured, placed facing the semi-conducting zone; forming in the at least one layer of front grid material a pattern reproducing a shape of the masking element and comprising etching of the layer of front grid material to eliminate the front grid material outside the pattern; and forming on free faces of the pattern a sacrificial spacer covering a first part of the semi-conducting zone.

Method for manufacturing a field effect transistor with auto-aligned grids

A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made of silicon nitride. Before flipping and bonding, a bounding layer, preferably made of amorphous silicon or polysilicon, is formed to bound drain and source areas. After flipping and bonding of the assembly on a second substrate, a second gate is formed in the gate cavity. At least partial silicidation of the bounding layer is then performed before the metal source and drain electrodes are produced.

Process for fabricating a field-effect transistor with self-aligned gates

A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.

Manufacturing process for a transistor made of thin layers

A method for insulating patterns formed in a thin film made of a first oxidizable semi-conducting material, with a thickness less than or equal to 20 nm and preferably less than or equal to 10 nm, successively comprises: The first and second semi-conducting materials can be identical and the step of selective formation of the additional layer can be performed by selective epitaxial growth of the free zones of the thin film.

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Grenoble, France

Bernard Previtali