Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Bernard Plessier

Alain C Pomet

Pierre-Yvan Liardet

Fabrice Romain

Laurent Sourgen

Tien-Dung Do

Brigitte Hennebois

In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Electronic device with encryption/decryption cells

A circuit and a method are provided for securing a coprocessor dedicated to cryptography. The disclosed circuit includes a scrambling register and an accessory input register to convey scrambling information in the form of electrical signals that disturb the visibility of certain electrical signals associated with confidential information such as digital keys.

Circuit and method for the securing of a coprocessor dedicated to cryptography

In the field of systems for the synchronization of modular electronic circuits, a system is provided for the coordinated activation of the modules. This system includes synchronization cells that have their pace set by a primary clock signal and deliver secondary clock signals controlled intermittently by the enabling signals to respectively activate the modules. The cells lock the state of each enabling signal associated with a regulator for regulating the periodicity of the change in state of each secondary clock signal and coordinating the changes in states of the secondary clock signals with one another. The system can be advantageously applied to electronic circuits having very high frequency data processing modules, especially those providing for the multiplexing of the transmissions of data carried out by each module.

System and method for coordinating activation of a plurality of modules through the use of synchronization cells comprising a latch and regulating circuits

A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers. Also provided is a coprocessor of the type that includes a series input terminal, a series output terminal, and computation elements located on at least one data path between the series input terminal and the series output terminal. Further, an IC chip card that includes a microprocessor, storage, and a coprocessor is provided.

Multiple access storage device

A Pfield operation defined according to the Montgomery method by P,(A, B),&equals;A*B*I mod N, where I is a determinable error, is implemented in a processor. The least significant word of the data elements A and N which are stored in elementary sub-registers are shifted twice. This eliminates delay cells in a processor used for executing the Pfield operation.

Method for the implementation of an elementary modular operation according to the Montgomery method

A division method and division circuit that can be integrated into a modular arithmetic coprocessor performs a reversal by word for the dividend and the quotient. This is done using a plurality of registers.

Method for the performance of an integer division with a modular arithmetic coprocessor

A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Sequential access memories

A sequential access memory working at the rate of a clock signal CK includes N register elements N, each storing an information bit. These register elements are divided into L groups, each comprising P elements that are series-connected and simultaneously activated or not activated (with P.times.L=N). The register elements of a given group are activated at least P times consecutively during a part of the time, and are not activated for the rest of the time. Accordingly, each group stores P consecutive information bits each from among the N bits arriving in serial form at the input of the memory. The advantage of the memory is that it enables a reduction in the dynamic energy consumption.

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Meyreuil, France

Bernard Plessier