Atrenta, Inc.

Hercules Technology Growth Capital, Inc.

Bernard Murphy

Mohamed Shaker Sarwary

Mohammad Movahed Ezazi

Shaker Sarwary

Manish Bhatia

Jun Yuan

Paras Mal Jain

Ashish Hari

Pratyush Kumar Prasoon

First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural analysis includes performing seed based recognition by identifying logic elements that indicate the existence of candidate FIFO circuitry and then exploring the candidate circuitry to completely verify the presence of a FIFO structure. Recognized FIFOs may be verified to ensure the proper generation of the full and empty flags.

Method for recognizing and verifying FIFO structures in integrated circuit designs

Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.

Method for clock synchronization validation in integrated circuit design

A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be found much later in the design or manufacturing cycle.

Chip development system enabled for the handling of multi-level circuit design data

A method for recognizing a pattern in a design of an integrated circuit (IC), comprising identifying a pattern correspondence element in a pattern instance. A pattern tree corresponding to the pattern instance is built. A list of candidate design correspondence elements in a design instance of the IC are built. Iteratively, for each design correspondence element in said list of candidate design correspondence elements each rank in a tree representation of said design instance built around said each design correspondence element is compared with corresponding rank in said pattern tree.

Pattern recognition in an integrated circuit design

Apparatus and method for handling of multi-level circuit design data

Growing community of inventors

San Jose, CA, United States of America

Bernard Murphy