International Business Machines Corporation

Bernard M Kemlage

John L Mauer, Iv

Richard C Joy

Cheng Tzong Horng

Jerry M Woodall

Shao-Fu S Chu

Robert W Broadie

Allen P Ho

Fred Barson

H Bernard Pogge

Karen A Fabricius

William C Wuestenhoefer

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

Isolation for high density integrated circuits

A method for making a monocrystalline integrated circuit structure is described. The monocrystalline silicon body is provided. There is formed thereon a layered structure of silicon dioxide, polycrystalline silicon and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form an oxide isolation pattern within the monocrystalline silicon body. If it is desired to form a semi-recessed oxide isolation there will be no etching of the monocrystalline silicon body in the openings. Should it be desired to form a full recessed oxide isolation there is etching of the monocrystalline silicon to a desired depth to form a substantially planar top surface of the monocrystalline with the recessed dielectric oxide isolation. The body is then oxidized until the desired oxide isolation pattern penetrates to the desired depth within the silicon body.

Method of manufacturing a minimum bird's beak recessed oxide isolation

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

A method for fabricating a high performance bipolar device having a shallow emitter and a narrow intrinsic base region is described. The method uses a minimum number of process steps. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A layer of polycrystalline silicon is deposited on the silicon substrate. The surface of the polycrystalline silicon is oxidized and the polycrystalline silicon is implanted with a base impurity. Silicon nitride and oxide layers are deposited on the polysilicon layer. An opening is made in the surface oxide layers and the silicon nitride layer to define the emitter area. The polycrystalline silicon is thermally oxidized to drive the base impurity into the substrate. The thermal oxide is removed in an isotropic etch to form a sidewall. The emitter impurity is ion implanted into the polycrystalline silicon in the emitter area and then driven into the substrate. The collector, base and emitter contact openings are made and the conductive metallurgy is formed.

Fabrication process for a shallow emitter/base transistor using same

A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described. The method includes depositing a polycrystalline silicon layer over a monocrystalline silicon surface in which the base and emitter regions of the transistor are to be formed. Boron ions are ion implanted into the polycrystalline silicon layer near the interface of the polycrystalline silicon layer with the monocrystalline silicon layer. An annealing of the layer structure partially drives in the boron into the monocrystalline silicon substrate. Arsenic ions are ion implanted into the polycrystalline silicon layer. A second annealing step is utilized to fully drive in the boron to form the base region and simultaneously therewith drive in the arsenic to form the emitter region of the transistor. This process involving a two-step annealing process for the boron implanting ions is necessary to create a base with sufficient width and doping to avoid punch-through. There is also described a method for forming NPN transistors in an integrated circuit.

Method of producing shallow, narrow base bipolar transistor structures

A method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.

Method of forming wide, deep dielectric filled isolation trenches in the

A chemical vapor deposition process wherein a silicon nitride barrier layer greater than about 50 Angstroms in thickness is formed over a silicon substrate and a low pressure chemical vapor deposition of a chlorosilane and a nitrous oxide oxidizing gas is used to form a silicon dioxide layer over the silicon nitride layer, where the silicon dioxide layer has a thickness between 2500 and 100,000 Angstroms. This process overcomes the problem of the low pressure chemical vapor deposition of silicon dioxide that does not use the silicon nitride layer. The problem is degradation of the silicon dioxide layer during subsequent oxidation cycles.

Prevention of low pressure chemical vapor deposition silicon dioxide

A method is described for forming a silicon dioxide layer on a semiconductor substrate in a furnace heated reaction zone of a chemical vapor deposition reactor having an input end for gaseous reactants wherein the silicon dioxide layer is not subject to degradation during subsequent oxidation cycles. A gaseous chlorosilane is mixed with nitrous oxide gas in the reactor. Oxygen gas is added, between about 0.25% to 10% by volume of total reactive gas mixture, to the chlorosilane and nitrous oxide gases in the reaction zone where the temperature is between about 800.degree. C. to 1200.degree. C. in a pressure of less than about 5 torr to deposit the silicon dioxide layer onto the substrate.

Low pressure chemical vapor deposition of silicon dioxide with oxygen

A process for producing light emitting diodes is disclosed. In the process a primer layer of GaP is pyrolytically deposited on a Si substrate with the resulting epitaxial film thickness being sufficient to form complete coalescence of the epitaxial nuclei, but thin enough to avoid cracks in the epitaxial layer due to stress induced by thermal expansion. The thickness is generally between 1-2.mu. . A second layer of GaP is then deposited using the standard halide transport process with thicknesses of 10-20.mu. with the graded addition of AsH.sub.3, until the particularly desired design composition of GaAsP is obtained. A constant layer of GaAsP is grown on the graded layer.

Two stage heteroepitaxial deposition process for GaAsP/Si LED's

A process for producing light emitting diodes is disclosed. In the process a primer layer of GaP is pyrolytically deposited on a Si substrate with the resulting epitaxial film thickness being sufficient to form complete coalescence of the epitaxial nuclei, but thin enough to avoid cracks in the epitaxial layer due to stress induced by thermal expansion. The thickness is generally between 0.1-10.mu.. A second layer of GaP is then deposited using the standard halide transport process with thicknesses of 2-5 .mu. or higher. In the case of GaP LED's the thickness is about 10-40 .mu., whereas for the case of GaAsP LED's the GaP thickness is 2-5 .mu. and this is then followed, through the addition of AsH.sub.3, with GaAsP graded from the GaP composition to the particularly desired design composition. The final composition is then maintained for 10-20 .mu..

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Kingston, NY, United States of America

Bernard M Kemlage