Intel Corporation

Other

Bernard Lint

David M Durham

Gilbert A Neiger

Uday R Savagaonkar

Prashant Dewan

Carlos V Rozas

Francis X Mckeen

Vincent R Scarlata

John I Garney

Ernie F Brickell

Simon P Johnson

Howard C Herbert

Gary L Graunke

Dion Rodgers

Michael A Goldsmith

Stephen R Van Doren

Stalinselvaraj Jeyasingh

Joseph Frank Cihula

Asher M Altman

Stephen J Tolopka

Don Alan Van Dyke

Jiang Tao Li

Shivnandan D Kaushik

Nhon Toai Quach

Jeffrey R Wilcox

Kushagra V Vaid

Lance E Hacking

Suresh K Marisetty

Mani Ayyar

Todd Aldridge Dutton

David I Poisner

Stephen H Gunther

Alon Naveh

Koichi Yamada

Gautham N Chinya

Devadatta V Bodas

Richard A Hankins

Perry H Wang

Asit K Mallick

Jamison D Collins

Siva Ramakrishnan

Ping Sager

A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

Method and apparatus to provide secure application execution

Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

System abstraction layer, processor abstraction layer, and operating system error handling

Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. In one embodiment, a lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing.

Enabling multiple instruction stream/multiple data stream extensions on microprocessors

A method and apparatus for global and local power management is herein described. Hardware within monitor/receives power management requests for any number of processing elements and adjusts global performance resources to change the global power state of all the processing elements or adjusts a local performance resource for a processing element to operate that processing element at a pseudo power state within the global power state.

Global and pseudo power state management for multiple processing elements

A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a previous period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.

P-state feedback to operating system with hardware coordination

Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

Hardware coordination of power management activities

Growing community of inventors

Mountain View, CA, United States of America

Bernard Lint