At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

At+t Corp.

Bell Telephone Laboratories

Bernard L Morris

Thaddeus John Gabara

Yehuda Smooha

Che-Tsung Chen

Lawrence A Walter

Jeffrey J Nagy

Lewis Emanuel Katz

Jorge Agraz-Guerena

CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Bipolar ESD protection for integrated circuits

An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.

Multi-voltage compatible bidirectional buffer

The number of active switching elements in a buffer is automatically varied to compensate for variations in the manufacturing process, operating temperature, and power supply voltage. For this purpose, a reference voltage which is proportional to the speed of a switching transistor is applied to an analog-to-digital (A/D) converter. The A/D converter may be implemented with a simple resistor divider and comparators, all of which can be made on-chip. The resistor dividers are chosen such that at worst-case slow conditions all the comparators have high outputs. As the process/temperature/voltage changes, the reference voltage also increases. This successively turns off sections of the switching transistor, thereby slowing down the response of the buffer. Since the control leads are digital, they are not susceptible to noise as they are routed around a chip full of noisy signals. The digital control signals may be latched, and the control circuitry powered down to zero for powersensitive applications.

Automatic control of buffer speed

Prior-art high speed TTL-to-CMOS input buffers consume a large amount of power supply current through the input transistors when the input voltage is held at a mid-range level between V.sub.DD and V.sub.SS (e.g., 2.0 volts). The inventive input buffer includes a resistance in series with the p-channel pull-up transistor on the input inverter, in order to limit this current. In addition, to retain high operating speed, a p-channel shunt transistor is placed in parallel with the resistance, and controlled by the buffer output signal. This shunt transistor effectively bypasses the resistance from the circuit when the buffer output goes low, thereby providing high operating speed.

CMOS input buffer with high speed and low power

A circuit is disclosed which converts CMOS logic input signals to ECL output signals. A pair of FETs, arranged as a conventional CMOS inverter, responds to the CMOS logic input signals and drives a bipolar transistor operating as a voltage follower. The emitter of the bipolar transistor serves as the output of the buffer providing the ECL output signals. A resistor having a predetermined resistance couples between a voltage source and the base of the bipolar transistor. First one of the pair of FETs couples a constant current source to the resistor and the base of the bipolar transistor when the buffer is supplying an ECL logical 'zero' logic signal. The current from the current source passing through the resistor establishes the ECL logical 'zero' output voltage. Second one of the pair of FETs shunts the resistor when the buffer is supplying an ECL logical 'one' output, allowing faster transitioning of the output of the buffer from an ECL logical 'zero' to a logical 'one'. Further, the current from the current source compensates for variations in the resistance of the resistor to assure a substantially constant difference between the ECL logical 'one' and the ECL logical 'zero' output voltages with variations in the resistance of the resistor from the manufacture thereof.

CMOS to ECL output buffer

An integrated circuit comprises a resistor that is formed by doping a semiconductor region that is defined by a layer, typically polysilicon, that also defines the gate electrode of field effect transistors in the integrated circuit. The well-controlled linewidth of features defined in this layer provides for tight resistor tolerance, and also allows the value of the resistor to track changes in other features defined by this layer.

Integrated circuit resistor

In various analog applications, it is desirable to have a known offset voltage at the input of a comparator, operational amplifier, or other type of differential stage. For example, in an ISDN receiver, the use of a desired offset allows for discriminating between signals having different amplitudes. In the present technique, a reference current, derived from a reference voltage (V.sub.ref) and on-chip resistor (R1) is used to set the currents through two input transistors, typically MOS transistors. An offset resistor (R0) in the source lead of one of the transistors produces a voltage drop that sets the offset at an input of the differential stage. The voltage drop across R0 is proportional to (V.sub.ref .times.R0)/R1. Since R0 and R1 are fabricated by the same process, their ratio is independent of temperature, process, etc. Therefore, a well-defined offset is obtained.

Differential circuit with controllable offset

A field effect transistor circuit generates a reference current that can obtain a desired temperature coefficient. The circuit is self-compensatory with respect to process variations, in that a 'slow' process will produce a higher than normal current, while a 'fast' process will give a lower one. This results in a tight spread of slew-rate, gain, gain-bandwidth, etc. in opamps, comparators, and other linear circuits. A simple adjustment in the circuit allows the temperature coefficient to be made positive or negative if so desired. An illustrative circuit is shown for CMOS technology, but can be applied to other field effect technologies.

Field effect transistor current source

A process for making dielectrically isolated silicon integrated circuits which use silicon oxide filled trenches to provide isolation is described. To minimize damage to the silicon, the trenches are filled by sequentially annealed oxidation process which involves alternately growing some oxide and then annealing to relieve stresses before growing more oxide.

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Allentown, PA, United States of America

Bernard L Morris