Xilinx, Inc.

Bernard L Grung

Moises Emanuel Robinson

Steven M Baier

Wayne L Walters

Michael J Gaboury

Yiqin Chen

A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

High speed serial I/O technology using an optical link

A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.

Phase lock loop and transconductance circuit for clock recovery

Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.

Digitally programmable phase-lock loop for high-speed data communications

A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.

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Eden Prairie, MN, United States of America

Bernard L Grung