Texas Instruments Corporation

Bernard John Fischer

Abbas Ali

Bradley David Sucher

Bhaskar Srinivasan

Sopa Chevacharoenkul

Khanh Quang Le

Collin White

Ashley Norris

An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

Anneal after trench sidewall implant to reduce defects

A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975&#xb0; C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100&#xb0; C. temperature ramp portion with an Oflow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.

A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) &#x2267;5 and a trench depth &#x2267;10 &#x3bc;m. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25&#xb0; C. sheet resistance &#x2266;100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.

In-situ doped polysilicon filler for trenches

A method of manufacturing a memory cell. The method comprises forming a memory stack. Forming the memory stack includes pre-treating an insulating layerin a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer. Forming the memory stack also includes depositing a silicon nitride layer on the pre-treated insulating layer.

Growing community of inventors

Richardson, TX, United States of America

Bernard John Fischer