Sony Corporation

Sony Electronics Inc

Other

Bernard James Griffiths

Derek Mellor

Frank E Hayden

Jeremy Chatwin

A metal oxide semiconductor field effect transistor (MOSFET) based voltage regulator circuit includes a first resistor, a second resistor, and a first MOSFET. A first gate terminal of the first MOSFET is connected to a second terminal of the first resistor and a first terminal of the second resistor. A first drain terminal of the first MOSFET is connected to a second terminal of the second resistor and a first output terminal of the voltage regulator circuit. The first MOSFET receives an input supply voltage at the first gate terminal of the first MOSFET, via the first resistor. The first MOSFET provides a first constant output voltage at the first output terminal based on a change in the input supply voltage.

Metal oxide semiconductor field effect transistor (MOSFET) based voltage regulator circuit

A system and method for effectively performing a clock signal distribution procedure includes a clock generator configured to generate one or more clock signals that include electronic timing information. A clock load utilizes the electronic timing information from the clock signals to synchronize appropriate system processes. Capacitive coupling means are provided in a series configuration for transferring the clock signals from the clock generator to the clock load in accordance with an alternating-current direct-drive technique.

System and method for effectively performing a clock signal distribution procedure

A system and method for effectively generating an electronic control signal includes a loop filter that has a first capacitor, a second capacitor, and a damping resistor. The first capacitor typically has a significantly greater capacitance than said second capacitor. A primary charge pump provides a primary charge current to the loop filter, and a damping charge pump provides a damping charge current to the loop filter. The loop filter responsively generates the electronic control signal for regulating the output frequency of a voltage-controlled oscillator. All components of the loop filter are sized to be implemented as part of an integrated circuit device.

System and method for effectively implementing a loop filter device

A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

System and method for implementing a swap function for an IQ generator

An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter.

System and method for implementing a digital phase-locked loop

A system and method for effectively implementing an IQ generator includes a master latch that generates an I signal and a slave latch that generates a Q signal. The master latch includes a master data circuit, a master latch circuit, and a master clock circuit. The slave latch includes a slave data circuit, a slave latch circuit, and a slave clock circuit. A cross-coupled current-source technique is used to compensate for certain device mismatches. A current source A generates an operating current A for the master clock circuit, the master data circuit, and the slave data circuit, and a current source B generates an operating current B for the slave clock circuit, the master latch, and the slave latch. In addition, resistors are utilized to provide fixed impedances to compensate for device mismatches between certain components in the master clock circuit and the slave clock circuit.

System and method for effectively implementing an IQ generator

A magnetic media storage system output circuit includes a filter for filtering an analog output signal from the storage media system before the analog output signal is provided to a read channel. Within the magnetic media storage system a read/write head reads data from a magnetic medium and provides an analog signal representing the data to an output circuit. The output circuit includes the filter for filtering the analog output signal and a pre-amplifier circuit for amplifying and transmitting the analog output signal to a read channel. Preferably, the filter has a linear frequency response and constant group delay below the cutoff frequency. Current on a write current control pin is used to control the cutoff frequency of the filter so that the cutoff frequency will track the data rate. An output signal from the storage media system output circuit is provided to a read channel.

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Ben Lomond, CA, United States of America

Bernard James Griffiths