Motorola Corporation

Freescale Semiconductor,inc.

Bernard J Pappert

Alfred Larry Crouch

Roger A Whatley

Ashok H Someshwar

John J Vaglica

Grady L Giles

Juxiang Ren

William C Bruce

Thomas K Johnston

Robert Scott Ruth

Matthew D Pressly

Clark Gilson Shepard

John K Eitrheim

Mark A Kearney

John Mark Boyer

William Clayton Bruce, Jr

Jeff L Warner

Robert Ash

A semiconductor device includes CMP dummy tiles () that are converted to active tiles by forming well regions () at a top surface of the dummy tiles, forming silicide () on top of the well regions, and forming a metal interconnect structure () in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Active tiling placement for improved latch-up immunity

Buffering circuitry ( ) uses pull-up slew rate control circuitry ( ) and pull-down slew rate control circuitry ( ) to control the rising and falling slew rates of an output signal ( ) provided by buffering circuitry ( ). Pull-up slew rate control circuitry ( ) and pull-down slew rate control circuitry ( ) may be used in an embodiment of buffering circuitry ( ) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry ( ) utilizes distributed resistive elements ( ) to provide improved electrostatic discharge protection. Buffering circuitry ( ) utilizes a low power level shifter ( ). Voltage reference generation circuitry ( ) may be used to provide a stable low power reference voltage VREF ( ).

Integrated circuit having buffering circuitry with slew rate control

In one embodiment, an integrated circuit ( ) has a contention detection circuit ( ) coupled to a tri-stateable output buffer ( ). The contention detection circuit ( ) provides a contention tri-state control signal ( ) to the tri-stateable output buffer ( ) in order to place it in a tri-stated condition when an external device ( ), such as a computer, supplies power to an input/output pad ( ) on the integrated circuit ( ). Thus, external and/or internal buffer contention is avoided when an external device ( ), such as a computer, supplies power to an input/output pad ( ) on the integrated circuit ( ).

Integrated circuit for handling buffer contention and method thereof

A method and apparatus that improves either power savings and/or DRAM system access bandwidth in an embedded DRAM device. The apparatus (200, 800, or 900) contains embedded DRAM memory devices (212, 802, or 902) which require refresh operations in order to retain data. As the memory devices (212, 802, or 902) are accessed by read and write system operations and by refresh operations, a set of history bits (204, 808, 904) are continually updated to indicate a level of freshness for the charge stored in various DRAM memory rows. When scheduled refresh opportunities arrive for each memory row in the embedded DRAM devices, the history bits (204, 808, 904) are accessed to determine if the refresh operation of a row of memory should be performed or if the refresh operation should be postponed until a subsequent refresh time period.

Method and apparatus for leveraging history bits to optimize memory

In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).

Buffering circuitry (10) uses pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) to control the rising and falling slew rates of an output signal (50) provided by buffering circuitry (10). Pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) may be used in an embodiment of buffering circuitry (10) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry (10) utilizes distributed resistive elements (89-91) to provide improved electrostatic discharge protection. Buffering circuitry (10) utilizes a low power level shifter (16). Voltage reference generation circuitry (18) may be used to provide a stable low power reference voltage VREF (42).

A Built-In Self Test (720) generates a BIST FAIL signal when a failure is detected at a specific address within a memory array (110). The address associated with the failure is stored in a latch (210). During normal operation, the address stored in latch (210) is compared to addresses being currently accesses. A HIT signal is generated when a match occurs. The HIT signal disables selection of the defective row in array (110). A redundant row select signal selects the redundant row (112) to replace the defective row.

Fuseless memory repair system and method of operation

A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.

Method and apparatus for performing operative testing on an integrated

A current monitor circuitry for detecting defects in a semiconductor device through performance of quiescent current testing. The circuitry for performing quiescent current testing may be implemented on chip or in an expendable portion of the wafer or a combination of both. In one embodiment, a quiescent current monitor unit interfaces with the circuit to be tested. The quiescent current monitor includes a sense amplifier and a level detector. The sense amplifier senses for a voltage differential and the level detector checks for a predetermined voltage rise. The voltage differences may be used for verification of specified circuit operations.

Quiescent current monitor circuit for wafer level integrated circuit

The present invention relates to a method (150) of construction of a scannable integrated circuit. The method includes forming a plurality of flip-flops on an integrated circuit where each flip-flop includes a system data transfer gate and a scan data transfer gate, the gates receiving control signals from a controller (152). A clock signal is routed to the flip-flops (154). Preferably, the flip-flops are placed in a manner to optimize the operation of the integrated circuit when in a system mode. The flip-flops are then coupled into scan chains such that the integrated circuit may operate at a scan mode frequency that is equal to or greater than a system mode frequency (156, 158, 160). An alternative method includes forming a plurality of input lines, a plurality of output lines, and a plurality of scan data paths such that each input line starts a balanced scan chain.

Method for creating a high speed scan-interconnected set of flip-flop

A barrel shifter comprises a first plurality of bit lines, a second plurality of bit lines and a plurality of switchable interconnections therebetween. A first subset of the switchable interconnections provide each of a set of desired shifts, while a second subset of the switchable interconnections duplicate certain of the first subset thereof and shorten the worst-case path lengths through the shifter. The first and second pluralities of bit lines may comprise interleaved high- and low-order bit lines of two data buses. Interface means may provide the interleaving function and also may provide means for accomplishing at least one shift in addition to the set of desired shifts. Sense amplifiers may be included for sensing voltage transitions on each bit line.

Barrel shifter

A two stage synchronizer circuit for synchronizing an asynchronous input signal with a local clock signal includes a reference inverter for generating a reference signal, a first sense amplifier for amplifying the difference between the reference signal and the asynchronous input signal, buffer inverters coupled to the output on the sense amplifier, a second sense amplifier coupled to the output of the buffer inverters, and an output inverter for delivering the desired synchronized signal. The reference inverter and the first and second buffer inverters have the same switch point so as to substantially reduce the probability of the generation of a meta-stable output. Furthermore, the first and second sense amplifiers and output inverter also have the same switch point as the reference inverter.

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Austin, TX, United States of America

Bernard J Pappert