International Business Machines Corporation

Bernard J Naudin

Jean L Calvignac

Jean-Pierre Lips

Jean-Marie L Munier

Jacques Feraud

Jean-Marc Millet

Warren D Bailey

Maurice Duault

Claude Pin

Bernard Brezzo

Denis Chevalier

Philippe Klein

Pierre Austruy

Joan Marie Bellinghausen

Eric Saint-Georges

Philippe Cuny

George M Calhoun

Oliver M Maurel

Richard H Waller

Edward Suffern

Kenenth J Barker

Eric Saint-George

Apparatus for recovering lost buffer contents in a data processing system uses a memory divided into a plurality of buffers provided with buffer control blocks, through which source and destination users exchange information. A buffer management circuit is responsive to requests from users for allocating buffers to source users in order that source users may store the information to be sent to the destination users. This circuit builds buffer queues and dequeues buffers from the queues to send the information contained therein to the destination users and releases the buffers afterwards. A time mark register is settable to n different values in a predetermined order. The value of the time mark register is changed at the expiration of a time period P. Each time a buffer is allocated to one user, the current value of the time mark register is written into a time mark field of the buffer control block and a state field is set to a first value (leased). When the buffer is released, the state field is set to a second value (released). The contents of the buffer control blocks are read at regular time intervals t after period P, and the state field of every buffer control block is tested to determine whether it is set to the second value. If not so set, the time mark field is compared with the value the time mark register had at the time t-xP, where x is a number such as 1&lt;x&lt;n, and the buffer is released in case of equality.

Apparatus for recovering lost buffer contents in a data processing system

The arbitrating method is based on the classification of the users into different categories, and the assignment to all users in a category of an identical privilege level which characterizes the interruption capability of the users in the category. A task performed by a selected user in a category can only be interrupted for granting access to the resource to a user in a category having a higher privilege level. Also a normal preference level is assigned to each user within a category, which determines the selection order of the users in the category. The privilege level of a user category combined with the preference level of each user constitutes the priority level of the user. The access to the resource is granted to a selected user having the highest priority level. If at least one user having a privilege level higher than the privilege level of the selected user, makes a request for the resource, the task of the selected user is interrupted and the interrupted user is assigned an interruption preference level which is higher than the normal preference levels of all other users in the category. A new user having the highest priority level is then selected after the resource is released by the interrupting user.

System for reassigning a higher priority to an interrupted user by

A communications system for transmitting data utilizes one or more picoprocessors located logically out of the main data path for conducting calculations and control functions in a fashion which is decoupled or separate from the main data path. In particular, the system utilizes multiple picoprocessors for performing buffer management and high performance buffer chaining processes out of the main data path so that the main data path may be continually used in parallel. In this manner, data transfer is enhanced by offloading functions and responsibilities from the main system processor and removing unnecessary traffic from the main data path.

Coupler for providing a high speed interface between a communication

This invention relates to a protocol implemented in a communication system for exchanging data and control messages between adapters to which are attached different users, and a shared memory subsystem comprising a depository storage, a manager of storage and a microprocessor. Such protocol enables the adapters to be the initiators of the transmission and reception of data by using the control lines that connect the manager of storage to all adapters in the same way as the data bus and the address bus. Moreover, the adapters slice the messages into data bursts to which are associated control words specifying the sizes, the owner and the position of the burst in the message. Consequently, those data bursts may be interleaved when transiting on the data bus without the intervention of the microprocessor for the routing, and they will be stored in or read from the depository storage according to the identification of the user in the control word. Therefore, only the shared memory needs to have a high capacity of storage, whereas the manager of storage and the adapters can operate with a reduced capacity of storage, and the time to send or to access a data burst is much more improved.

Method for exchanging messages between a shared memory and communication

A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.

Mechanism for transferring messages between source and destination users

The subject device manages the access to message queues in a memory (6) by an enqueuer 2 and a dequeuer 7 when the enqueuer has priority over the dequeuer. It solves the contention problem raised when the dequeuer dequeues the last message from a queue while the enqueuer is enqueuing anew one. A queue control block QCB and queue status bits E, A, D are assigned to each queue and stored in memories 20 and 22. Each time dequeuer 7 performs a dequeuing operation it sets its D bit (dequeuer active) before updating the queue head field in the QCB block. When the enqueuer performs an enqueuing operation it sets an abort bit A, if it finds the D bit active and E bit active indicating that the queue contains at least one message to warn the dequeuer that it has to abort its process if it is dequeuing the last message from the queue.

Device for controlling the enqueuing and dequeuing operations of

A distribution mechanism includes a scheduling device which partitions a common timing signal with a period T into n slots of t duration each, a configuration table having n addressable locations with each of the n locations storing communication control information and addressable by slot numbers generated by the scheduling device and a distribution buffer device (2) having at least a first and a second part, with each part having n addressable locations addressed by control information provided by the configuration table during each slot period to cause an interface involved in the to be established communications during a selected slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot generated by the schedule means.

Distribution mechanism for establishing communications between user

The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical '1' bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N&lt;n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical '1's' as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).

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Saint Laurent Du Var, France

Bernard J Naudin