Fairchild Semiconductor Corporation

Bernard J Czeck

Joseph Andrew Yedinak

Douglas Joseph Lange

Jack Edward Wojslawowicz

Dwayne S Reichl

Robert Baran

An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

Voltage divider field plate termination with unequal fixed biasing

An IGBT has striped cell with source stripes continuous or segmented along the length of the base stripe The opposite stripes are periodically connected together by the N&plus; contact regions to provide channel resistance along the width of the source stripes . For continuous stripes the resistance between two sequential contact areas is greatest in the middle and current concentrates near the source contact regions The wider the spacing between the contacts the larger the resistive drop to the midpoint between two N&plus; contacts

IGBT with channel resistors

An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, particularly at the transition between the N buffer & N drift region.

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Mocanaqua, PA, United States of America

Bernard J Czeck