Mstar Semiconductor, Inc.

Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Philips Electronics North America Corporation

Philips Semiconductors Inc.

Ylsi Technology, Inc.

Nxp B.v.

Bernard Ginetti

Zhongxuan Zhang

Khurram Muhammad

Dennis Mahoney

Laurent Souef

Jerome Bombal

Chih-Ming Hung

Philippe Gaglione

Ming-Yu Hsieh

Remi Butaud

Christian Zotier

Olaf Granzow

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

Multiplexed configurable sigma delta modulators for noise shaping in a 25-percent duty cycle digital transmitter

Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.

Parallel multibit digital-to-digital sigma-delta modulation

In one embodiment, a sequence of a plurality of pairs of in-phase (I) and quadrature (Q) modulated signal samples are applied to a radio frequency digital-to-analog converter (RFDAC) for upconversion. A phase of a local oscillator (LO) signal supplied to the RFDAC is selected according to a quadrant determined by signs of a given pair of I and Q modulated signal samples. The selected phase of the LO is supplied to the RFDAC for use in upconverting the sequence of I and Q modulated signal samples. In another embodiment, a current steering DAC is used for directly upconverting the I and Q modulated signal samples. A clock signal at four times the LO frequency is supplied to a counter and to the current steering DAC. One of the I and Q modulated signal samples and negative I and negative Q modulated signal samples is selected for supply to an input of the current steering DAC based on a count state of the counter.

Digital quadrature transmitter using generalized coordinates

An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.

Digital modulation with arbitrary input sampling and output modulation frequencies

The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal.

NMOS buffer for high-speed low-resolution current steering digital-to-analog converters

The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.

1-bit cell circuit used in a pipelined analog to digital converter

A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator. A GSM phone comprises a clock configured to produce a first clock signal; a delay element coupled to the clock to produce a second clock signal by delaying the first clock signal; a multiplexer coupled to the clock and to the delay element to select between the clock and the delay element; a random number generator coupled to the multiplexer wherein the multiplexer generates a jittered clock signal by switching between the first clock signal and the second clock signal responsive to the random number generator; and a plurality of GSM phone components respectively coupled to the multiplexer to use the jittered clock signal as an input clock for the component.

Clock circuit, GSM phone, and methods of reducing electromagnetic interference

A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port. A method is also provided for reducing layout area during test insertion when using an ATPG program to design an integrated circuit having design-for-testability features.

Computer implemented circuit synthesis system

Design for test area optimization algorithm

An improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC is described wherein the testability is independent of the core logic of that IC, which does not require the dedication of any pin solely to the testing of that IC. A uniform analog test access port design simplifies chip layout, greatly reduces the nunber of MUXed pins required, and allows generation of an analog test program for the total chip which is a simple concatenation and re-use of the individual analog cell test programs.

Analog test access port and method therefor

A digital-to-analog converter with differential output voltage includes a resistor string with high and low reference voltages end nodes and with nodes located between adjacent resistors of the string, first switches of a first analog multiplexer for deriving first divided voltages from first nodes of the resistor string, second switches of a second analog multiplexer for deriving second divided voltages from second nodes of the resistor string, and a decoder device receiving a digital signal. The decoder device is coupled to the first switches for selecting the first switches according to a first code derived from a first bit portion of the digital signal, and the decoder device is coupled to the second switches for selecting the second switches according to a second code derived from a second bit portion of the digital signal different to the first bit portion, whereby a selected first divided voltage and a selected second divided voltage define a selected differential output voltage of the converter. The decoder device includes two separate decoders each for deriving the first and second codes, and the first multiplexer and second multiplexer are switched only one at a time.

Differential voltage digital-to-analog converter

A digital to analog converter (DAC) offset autocalibration system in a digital synthesizer integrated circuit. The present invention includes a DAC coupled to a filter. The input of the DAC accepts digital values for conversion to an analog signal. The output of the DAC is coupled to the input of the filter. The filter smoothes the analog signal received from the DAC. A switch is coupled to the filter output to receive the analog signal. A comparator is coupled to the switch. The input of the comparator receives the analog signal from the filter output via the switch. An autocalibration control circuit is coupled to the output of the comparator, to the switch, and to the DAC. The autocalibration control circuit is adapted to input a value to the DAC in order to determine an offset correction from the output of the comparator and adjust the analog signal using the offset correction.

Digital to analog converter offset autocalibration system in a digital

A low voltage digital-to-analog converter (DAC) uses a resistor string to divide a supply voltage. The voltage output for the DAC is fixed at an intermediary node in the resistor string, and NMOS and PMOS transistors are used to switch in V.sub.SS and V.sub.DD respectively to nodes in the resistor string such that the NMOS and PMOS transistors are operated where they are most conductive. A decoder is used to decode the digital input to control the switches. One switch from each set of NMOS and PMOS transistors is activated for a given input, or thermometric decoding of the input is used to activate more than one switch from each set to preserve monotonicity. In an alternative embodiment, when matching of the resistors can be assumed, a two-step decoding process is used. An LSB decoder decodes the least significant bits of the digital input and controls how V.sub.DD is applied to a bank of LSB resistors through PMOS transistors, and how V.sub.SS is applied to a second bank of LSB resistors through NMOS transistors. The output from each of these LSB banks lead into to a first MSB bank of resistors and a second bank of MSB resistors, respectively. An MSB decoder decodes the most significant bits of the digital input and controls how the output from the first LSB bank is applied to the first bank of MSB resistors through PMOS transistors, and how the output from the second LSB bank is applied to the second bank of MSB resistors through NMOS transistors. Each MSB resistor is greater than seven LSB resistors in series, and the maximum impedance difference between switches is smaller than an LSB resistor in order to preserve monotonicity of the DAC.

Low voltage digital-to-analog converter

An interstage amplifier for a pipelined analog-to-digital converter comprises an operational amplifier (50) having two balanced amplifying paths; a first pair of capacitors (55,58); a second pair of capacitors (56,57); and switching means (59-62) connected to the capacitors and said amplifier and arranged for: (i) during a first phase, enabling the first pair of capacitors (55,58) to receive a respective first sample of a first signal; (ii) during a second phase, enabling the second pair of capacitors (56,57) to receive a second sample of the first signal; (iii) during a third phase, enabling the first pair of capacitors (55,58) to receive a first sample of a second or reference signal and to enable charge to be transferred from each of the first pair of capacitors by way of a respective path of the amplifier to a respective one of the second pair of capacitors; and (iv) during a fourth phase, enabling the second pair of capacitors (56,57) to receive a second sample of the said second or reference signal and to enable charge to be transferred from each of the second pair of capacitors by way of a respective path of the amplifier to the respective one of the first pair of capacitors. The arrangement provides first-order correction of capacitor mismatch.

Pipelined analog to digital converters and interstage amplifiers for

A digital-analog converter incorporates an array of current source cells connected at the output to a load as a function of an input code subdivided into H and V values, which are most significant bit (MSB) and least significant bit (LSB), respectively. The input code is converted into thermometric codes, respectively HT and VT, whose logic inverses are respectively horizontally and vertically routed to the array. Each position cell (h, v) in the array comprises a first and a second P type metal oxide semiconductor field effect transistor connected in series, and the series is in parallel with at least one third P type metal oxide semiconductor field effect transistor.

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Antibes, France

Bernard Ginetti