Semiconductor Components Industries, LLC

Ami Semiconductor Belgium Bvba

Bernard Gentinne

Francois Laulanet

Bart De Cock

Geert Vandensande

Bart DeCock

A method and module for monitoring a voltage of a power cell, sampling and holding a voltage of the power cell, and balancing a voltage of the power cell. In accordance with an embodiment, an interface circuit is capable of operation in a plurality of operating modes. In accordance with another embodiment, the interface circuit is coupled to a filter section.

Monitor and control module and method

The invention relates to a signaling system for use in a system for monitoring and/or controlling a stack of power cells. The stack of power cells is series connected, i.e. the negative terminal of one power cell is connected to the positive electrode of the adjacent power cell. A monitoring device is associated with each power cell to monitor characteristics of the power cell (temperature, voltage). Every monitoring device is powered by the power cell it is associated. The monitoring device monitors the status of the cell (e.g. it measures the difference of potential between the positive terminal and the negative terminal of that cell but it may also measure the temperature of the power cell, the pH of the electrolyte if the power cell Ci is a battery, etc. and communicates information on the status of the cell to other monitoring devices. The monitoring devices are daisy chained. Data cannot be exchanged between a monitoring device from one cell and a monitoring device from another cell without that the data sent by the one device transits by the other devices in the chain.

Power cell monitoring

A comparator has first and second current paths, each passing from an input through a transistor, through a current source to ground, the second current path also having a reference voltage drop element coupled in series with the second input. The gates of the transistors are coupled to form a current mirror. The reference voltage drop element enables higher voltages to be input and compared to higher thresholds above an internal supply voltage level without the need for dividing resistors to reduce the input voltage. Avoiding such resistors means the power dissipation and the silicon area used can be kept lower. ESD vulnerability is reduced since the inputs are not coupled to gates of MOS transistors. Overvoltage protection across the source and gate of the second transistor can be added.

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Brussels, Belgium

Bernard Gentinne