Thomson-Csf

Bernard Dias

Arnaud Du Chene

Gerard Bergeon

The invention pertains mainly to a processor for the calculation of the discrete Fourier transform, comprising a real-time testing device. The device according to the invention uses the theorem of Parseval to ascertain that the processor is working properly. The device according to the invention uses, for example, an adder and a multiplier to calculate either the discrete Fourier transform or the members of the equation. Thus, by using temporal redundancy, the complexity, area and price of the processor are reduced. The invention is applied mainly to the calculation of spectra.

Discrete fourier transform calculating processor comprising a real-time

A device and a method are used to test integrated circuits, especially P.L.A.s. The possible faults of a circuit to be tested are determined including logic faults caused by the physical structure and relative position of the circuit elements in the integrated logic circuit. On the basis of the faults, a set of test vectors is determined, each fault modifying at least one of the test vectors applied to the circuit to be tested. It is possible to use test vectors which are modified by the greatest number of possible faults. By determining the test vectors on the basis of the faults which are to be detected, the tests can use a small number of vectors while, at the same time, there is certainty that it will be possible to detect all the faults in a given circuit. Advantageously, a hierarchically-organized set of cells is determined with certain cells consisting of small cells. The method and device can be used to test P.L.A.s by using a small number of test vectors, and are applicable to testing integrated circuits and P.L.A.s.

Device and method for the generation of test vectors and testing method

A device for the testing of electrical circuits and a circuit comprising the said device are disclosed. The testing device is used to test electrical circuits by the generation of test vectors and the compression of the signal at the output of the device to be tested. The device of the present invention uses the same shift register, certain cells of which are looped at the input, by means of an exclusive-OR logic gate, to generate test vectors and perform signature analysis. Thus it is possible to test electrical circuits themselves as well as the input/output buses. The invention can be applied, in particular, to the testing of computers, microprocessors, memories, fast Fourier transform calculators, adders, multipliers, combinational logic systems or circuits including combinational logic systems or circuits that have internal memorizing devices.

Growing community of inventors

Paris, France

Bernard Dias