International Business Machines Corporation

Bernard Desrosiers

Andre R Steimle

Didier R Louis

Catherine Godefroy

Patrick Lampin

Yves Langlois

Didier Pinchon

Louis Didier

Pascal Henri Legras

In a telecommunication system adapted to exchange n-bit frames according to a dynamic time division multiplexing access method for a maximum of N accessible channels, the use of a shadow time slot assignment table is eliminated by use of a circuit that includes (a) an n&#xd7;p memory block to store a time slot assignment table which describes the different time slot assignments by specifying which logical channel each bit position of an n-bit frame belongs to, (b) a register having N fields with a granularity of one bit, each bit indicates the status of the corresponding logical channel associated thereto, and (c) a logic circuit connected to the memory block and register that enables or disables the transmission of the logical channel identifier to a time slot assignor depending on the status bit value.

Dynamic time division multiplexing circuit without a shadow table

A parallel to serial conversion circuit is disclosed. The circuit is used for converting parallel bits representing a plurality of words into serial bits. The circuit consists of storing means which comprises a plurality of word locations for temporarily storing the plurality of words at a parallel clock rate, and serialization means connected to the storing means for converting the parallel bits into serial bits at a serial clock rate. Each of the plurality of word locations is organized as a plurality of cells for storing each, one bit. Moreover the serialization means comprises parallel pointing means connected to the storing means for pointing to the plurality of words locations synchronously to the parallel clock, and serial pointing means also connected to the storing means for pointing to the plurality of cells synchronously to the serial clock. Filling indicator means are connected both to the parallel pointing means and to the serial pointing means for generating a status signal indicating the status empty or full of the storing means such that the serial pointing means is responsive to the status signal for successively pointing to the plurality of cells when the status is full.

Asynchronous serialization/deserialization system and method

An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.&lt;1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to 'zero' and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS). Also incorporated is a leading zero detector/encoder circuit and a second circuit arrangement operative to perform pipeline operations on exponents connected to an encoder circuit whose output controls the aligner circuit and a selector circuit driven by the outputs of the detector/encoder circuit and encoder circuit whose output controls the normalizer circuit; a xi determining circuit that generates the xi mantissa on a xi-BUS connected to the first circuit arrangement such that: mantissa xi=0=K(1) K(2) 1 0 . . . , 0, and a read-only memory to store the F(xi) values whose output is connected to inputs of the first and second circuits for the respective mantissa and exponent parts of F(xi).

Apparatus for argument reduction in exponential computations of IEEE

A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.

System for optimizing argument reduction

A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0. In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the 'carry out' output. The 'Force Carry' input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.

Growing community of inventors

Boissise le Roi, France

Bernard Desrosiers