National Semiconductor Corporation

Micrel, Incorporated

Bernard D Miller

Robert C Dobkin

Silvo Stanojevic

Tim D Isbell

Lawrence R Sample

A self-aligned MOS transistor is described in which the gate-drain underdiffusion length is substantially greater than the gate-source underdiffusion length, resulting in a relatively high gate-drain capacitance. This is accomplished by driving in the drain dopants to have a greater diffusion depth and underdiffusion length than that of the source dopants. The increased gate-drain capacitance obviates the need to provide a separate gate-drain capacitor where increased gate-drain capacitance is desired.

MOS transistor having increased gate-drain capacitance

A process is described for providing a self-aligned MOS transistor having a selectable gate-drain capacitance. In a self-aligned process for forming a PMOS transistor, a polysilicon layer is etched to expose portions of an n-type substrate in which it is desired to form p+ drain regions. A deep p.sup.+ drain region is then formed in the surface of the substrate so as to have a large diffusion under the polysilicon layer. This large diffusion results in a high gate-drain capacitance. The polysilicon layer is further etched to form a gate. A self-aligned source is then formed using a separate, relatively shallow p+ diffusion. The selectable gate-drain capacitance obviates the need to form separate capacitors on the substrate to use as gate-drain capacitors.

A circuit and structure intended for use in CMOS IC designs acts to protect signal lines against ESD. An array of three transistors is connected so that the voltage pulse that appears on the signal line as a result of ESD, forces at least one transistor into conduction. The circuit responds equally to positive and negative pulses and is, therefore, symmetrical, and independent of bias or supply potentials. In the absence of an ESD pulse the circuit draws a very low leakage current and, therefore, has very little effect upon normal IC operation.

Electrostatic discharge integrated circuit protection

An IC thermal shutdown circuit is based upon the thermal characteristics of a reverse biased PN junction diode. The leakage current, at bias levels below breakdown, is closely related to the high temperature IC performance limit. A hysteresis introducing circuit produces reliable switching at predetermined levels to shut down the IC when the maximum temperature limit is reached.

Adaptive thermal shutdown circuit

In an instrumentation amplifier a differential input is provided, one side of which is connected to an instrument ground that is remote from the amplifier power supply ground. The remote ground can, under some conditions, operate at a potential that is outside the potential span of the amplifier power supply. Such common mode potentials are difficult to cope with when the difference exceeds about 0.6 volt. The circuit employs a pair of transistors biased to equal current densities. The emitters constitute the circuit input terminals. Means are provided to adjust the transistor collector to base voltage to establish a constant predetermined current. The transistor that is to be connected to the remotely grounded input has a resistor coupled between emitter and base to produce a reference current. A resistor connected between the transistor bases will then assume a potential equal to the emitter potential difference. A current mirror reproduces the base resistor current at the amplifier output terminal. Since the transistor emitters can operate at several volts below ground, an extended common mode range is available.

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San Jose, CA, United States of America

Bernard D Miller