International Business Machines Corporation

Bernard Charles Drerup

Barry Joe Wolford

Guy L Guthrie

Richard Gerard Hofmann

Lakshminarayana Baba Arimilli

James Norris Dieffenderfer

Thomas Andrew Sartorius

Jeffrey A Stuecheli

William John Starke

Richard Nicholas

Derek E Williams

Thomas Philip Speier

Jaya Prakash Ganasan

Jody B Joyner

John David Irish

Mark Anthony Check

Victor Roberts Augsburg

Michael Grassi

Alexander Michael Taft

Richard Siegmund, Jr

Ravi Kumar Arimilli

Brian William Thompto

Jerry Don Lewis

Mohit Karve

Luis E De La Torre

Michael Steven Siegel

Hugh Shen

Giora Biran

Sundeep Chadha

Hanhong Xue

Jaya Prakash Subramaniam Ganasan

Paul Frank Lecocq

Prasanna Srinivasan

Parag Birmiwal

John Edward Dickol

Jyoti Gupta

Charles Ray Johns

Gary Dale Carpenter

Russell Dean Hoover

Richard James Eickemeyer

Phillip G Williams

Bradly George Frey

Thuong Quang Truong

Charles Francis Marino

David John Krolak

Scott Douglas Clark

Ram Raghavan

George W Rohrbaugh, Iii

Richard Nicholas Iachetta, Jr

Luke Murray

Wendel Glenn Voigt

Sean Eugene Curry

Hai Quang Bui

Sahil Sabharwal

Claude Basso

Colin Beaton Verrilli

Harm Peter Hofstee

Christoph Raisch

Brian Mitchell Bass

Sanjeev Ghai

James Michael Stafford

Ronald Nick Kalla

Piyush Chaudhary

David W Cummings

Robert Michael Dinkjian

Jan-Bernd Themann

James C Peterson

Victor R Angsburg

Joseph John McGill, Iv

Victor E Augsburg

The present disclosure may include a processor that uses idle caches as a backing store for a boot code. The processor designates a boot core and an active cache from a plurality of cores and a plurality of caches. The processor configures remaining caches from the plurality of caches to act as a backing store memory. The processor modifies the active cache to convert cast outs to a system memory into lateral cast outs to the backing store memory. The processor copies a boot image to the backing store memory and executes the boot image by the boot core.

Using idle caches as a backing store for boot code

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric coupled to the system memory and the multiple vertical cache hierarchies. Based on a request of a requesting processor core among the plurality of processor cores, a master in the multiprocessor data processing system issues, via the interconnect fabric, a read-type memory access request. The master receives via the interconnect fabric at least one beat of conditional data issued speculatively on the interconnect fabric by a controller of the system memory prior to receipt by the controller of a systemwide coherence response for the read-type memory access request. The master forwards the at least one beat of conditional data to the requesting processor core.

Speculative delivery of data from a lower level of a memory hierarchy in a data processing system

A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.

Controlling issue rates of requests of varying broadcast scopes in a data processing system

A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

Distribution of injected data among caches of a data processing system

A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.

Targeting of lateral castouts in a data processing system

A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.

Data processing system having masters that adapt to agents with differing retry behaviors

A technique for operating a data processing system that implements a split transaction coherency protocol that has an address tenure and a data tenure includes receiving, at a data source, a command (that includes an address tenure for requested data) that is issued from a data sink. The data source issues a response that indicates data associated with the address tenure is available to be transferred to the data sink during a data tenure. In response to determining that the data is available subsequent to issuing the response, the data source issues a first data packet to the data sink that includes the data during the data tenure. In response to determining that the data is not available subsequent to issuing the response, the data source issues a second data packet to the data sink that includes a data header that indicates the data is unavailable.

Split transaction coherency protocol in a data processing system

A method comprises a cache manager receiving reference attributes associated with network data and selecting a replacement data location of a cache to store cache-line data associated with the network data. The replacement data location is selected based on the reference attributes and an order of reference states stored in a replacement stack of the cache. The stored reference states are associated with respective cached-data stored in the cache and based on reference attributes associated with respective cached-data. The reference states are stored in the replacement stack based on a set of the reference attributes and the stored reference states. In response to receiving reference attributes, the cache manager can modify a stored reference state, determine a second order of the state locations, and store a reference state in the replacement stack based on the second order. A system can comprise a network computing element having a cache, a cache manager, and a replacement stack. The cache manager can perform the method with respect to network data received by the network computing element.

Cache data replacement in a networked computing system using reference states based on reference attributes

A method comprises receiving input reference attributes from a data reference interface and selecting a replacement data location of a cache to store data. The replacement data location is selected based on the input reference attributes and reference states associated with cached-data stored in data locations of the cache and an order of state locations of a replacement stack storing the reference states. The reference states are based on reference attributes associated with the cached-data and can include a probability count. The order of state locations is based on the reference states and the reference attributes. In response to receiving some input reference attributes, reference states stored in the state locations can be modified and a second order of the state locations can be determined. A reference state can be stored in the replacement stack based on the second order. A cache can comprise a data reference interface, reference attributes, reference states, cached-data locations, a replacement stack, and a cache manager. The cache manager can perform the method.

Cache line replacement using reference states based on data reference attributes

A set-associative cache memory includes a plurality of ways and a plurality of congruence classes. Each of the plurality of congruence classes includes a plurality of members each belonging to a respective one of the plurality of ways. In the cache memory, a data structure records a history of an immediately previous N ways from which cache lines have been evicted. In response to receipt of a memory access request specifying a target address, a selected congruence class among a plurality of congruence classes is selected based on the target address. At least one member of the selected congruence class is removed as a candidate for selection for victimization based on the history recorded in the data structure, and a member from among the remaining members of the selected congruence class is selected. The cache memory then evicts the victim cache line cached in the selected member of the selected congruence class.

Victim cache line selection

Techniques are disclosed for identifying data streams in a processor that are likely to and not likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization are deprioritized. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level, prefetch utilization, and memory resource utilization.

Prefetch performance

A set-associative cache memory includes a bank of counters including a respective one of a plurality of counters for each cache line stored in a plurality of congruence classes of the cache memory. Prior to receiving a memory access request that maps to a particular congruence class of the cache memory, the cache memory pre-selects a first victim cache line stored in a particular entry of a particular congruence class for eviction based on at least a counter value of the victim cache line. In response to receiving a memory access request that maps to the particular congruence class and that misses, the cache memory evicts the pre-selected first victim cache line from the particular entry, installs a new cache line in the particular entry, and pre-selects a second victim cache line from the particular congruence class based on at least a counter value of the second victim cache line.

Counter-based victim selection in a cache memory

In one embodiment, a set-associative cache memory has a plurality of congruence classes each including multiple entries for storing cache lines of data. The cache memory includes a bank of counters, which includes a respective one of a plurality of counters for each cache line stored in the plurality of congruence classes. The cache memory selects victim cache lines for eviction from the cache memory by reference to counter values of counters within the bank of counters. A dynamic distribution of counter values of counters within the bank of counters is determined. In response, an amount counter values of counters within the bank of counters are adjusted on a cache miss is adjusted based on the dynamic distribution of the counter values.

In at least some embodiments, a processor core executes a sending thread including a first push instruction and a second push instruction subsequent to the first push instruction in a program order. Each of the first and second push instructions requests that a respective message payload be pushed to a mailbox of a receiving thread. In response to executing the first and second push instructions, the processor core transmits respective first and second co-processor requests to a switch in the data processing system via an interconnect fabric of the data processing system. The processor core transmits the second co-processor request to the switch without regard to acceptance of the first co-processor request by the switch.

Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread

Growing community of inventors

Austin, TX, United States of America

Bernard Charles Drerup