U.S. Philips Corporation

Other

Koninklijke Philips Corporation N.V.

Koninlijke Philips Electronics N.v.

Bernard Bru

Marc A Duranton

Valerie Vier

Loic Geslin

A data-processing arrangement &lsqb;DPA&rsqb; is capable of processing different types of data &lsqb;I, II, III&rsqb; such as, for example, luminance (Y) and chrominance (UV) pixels from various pictures. The data-processing arrangement &lsqb;DPA&rsqb; comprises a controller &lsqb;MCP&rsqb; for executing a set of program items &lsqb;PI&rsqb;. A program item &lsqb;PI&rsqb; causes the data-processing arrangement &lsqb;DPA&rsqb; to fetch and process &lsqb;F&PR&rsqb; a block of data &lsqb;DB&rsqb; of a certain type &lsqb;I, II, III&rsqb;. The data-processing arrangement &lsqb;DPA&rsqb; further comprises an interface &lsqb;INT&rsqb; for temporarily storing a block of data &lsqb;DB&rsqb; in one of a plurality of memory sections &lsqb;MS&rsqb;. The memory section in which the block of data &lsqb;DB&rsqb; is stored is defined by the position that the program item &lsqb;PI&rsqb; for the block of data &lsqb;DB&rsqb; has within in the set of program items.

Data-processing arrangement for processing different types of data

A data-processing arrangement comprises a plurality of elementary circuits such as processing circuits &lsqb;PRC&rsqb; and memory circuits &lsqb;MEM&rsqb;. The data-processing arrangement further comprises a controller &lsqb;MCP&rsqb;. The controller &lsqb;MCP&rsqb; is programmed to successively apply, in response to a task-initialization data &lsqb;TID&rsqb;, control data &lsqb;CD&rsqb; to different subsets of elementary circuits. This causes the data-processing arrangement to process a block of data &lsqb;DB&rsqb; in accordance with a certain data-processing chain &lsqb;DPC&rsqb;. Each subset of elementary circuits implements a different element &lsqb;E&rsqb; of the data-processing chain &lsqb;DPC&rsqb;.

Data-processing arrangement comprising a plurality of processing and memory circuits

A method is described for addressing units (FU FU FU ) amongst a plurality of units having different addresses (ADD ADD ADD ) by use of an address word (AW), the addresses and the address word being composed of address elements. A tag word (TW) is transmitted to the plurality of units, the tag word defining which address elements of the address word are significant (S) and which address elements of the address word are non significant (X). The address word and the addresses of the units are compared and, a unit is addressed if the significant elements of the address word match the corresponding elements of the unit's address.

Method of addressing a plurality of addressable units by a single address word

A data processing arrangement comprises various data processors (P) and a memory arrangement (MA) for supplying input data (Di) to the data processors (P) and for storing output data (Do) from the data processors (P). The following steps are alternately carried out: a configuring step (CS) and a processing step (PS). In a configuration step (CS), the data processing arrangement is configured such that each data processor (P) will process a block (B) of data contained in the memory arrangement (MA) and then stop processing data. In a processing step (PS), the blocks (B) of data are processed in the respective data processors (P). A subsequent configuring step (CS) is carried out only when each data processor (P) has processed its block (B) of data (&forall;P: B&equals;PROC>CS). Such a data processing arrangement allows great versatility because different data processing chains can be realized without this requiring relatively complicated software.

Data processing using various data processors

Device for decoding encoded digital signals corresponding to n different types of data, for example audio, video or graphic data. Such decoder includes, upstream of the decoder itself, an input interface which includes a storage sub-assembly composed of n parallel registers for receiving said data. The input interface also includes, between such registers and an external DRAM-type memory of the decoder, a series arrangement of a first buffer memory (43) for storing the contents of a register as soon as one of them is full, and a second buffer memory (44) constituted by n parallel blocks (45a, 45b, . . . ) for storing, per type of data, the contents of the first buffer memory. At the output of such storage blocks, the corresponding requests for access are carried out by a synchronizing clock (47) via an arbiter so as to transmit the contents of the blocks to the external DRAM memory.

Growing community of inventors

Limeil-Brévannes, France

Bernard Bru