Gm Global Technolgoy Operations, Inc.

Bernard A MacIver

Kailash Chandra Jain

James C Erskine

Eugene Greenstein

John C Bierlein

Stephen J Valeri

A resonant bridge microaccelerometer is formed using patterned Silicon-on-Insulator (SOI) material. A buried layer is formed in the silicon substrate using preferably oxygen ion implanting techniques. A predetermined proof mass is subsequently formed by selective deposition of an appropriate material on an epitaxially grown layer of silicon generally over the buried layer. The buried layer is subsequently removed by a hydrofluoric acid etch, thereby forming a gap generally everywhere therebetween the proof mass and the supporting silicon substrate, and delineating the resonant microbridges within the microaccelerometer.

Method and product for fabricating a resonant-bridge microaccelerometer

JMOS depletion mode transistors include back-to-back junctions in the doped polysilicon layer that serves as the gate. The polysilicon layer includes a first region of the same conductivity type as the channel in contact with the channel, and a second region, of the same conductivity type as the channel and to which the gate potential is applied, spaced apart by a region of the opposite conductivity type that serves as a sink for minority carriers in the channel. Both buried oxide layer and recessed gate JMOS transistors are included.

JMOS transistor utilizing polysilicon sinks

A process for forming a buried patterned silicon oxide layer in a silicon chip in which the layer is formed by implanting oxygen into the chip through a mask of silicon oxide on the surface of the silicon chip. The silicon oxide mask is formed to have essentially vertical side walls by interposing an irradiation step between a pair of isotropic wet etching steps in its formation.

Process for forming in a silicon oxide layer a portion with vertical

A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.

High voltage depletion mode MOS power field effect transistor

An insulated gate field effect transistor of the depletion mode type has a recessed gate structure with opposed gate sections on opposite sides of adjacent bar-like structures defined in a channel region. An opposite conductivity-type island in the channel region is electrically connected to the transistor gate electrode. A voltage applied to the gate electrode generates an electric field effect which extends from the opposed gate sections into said bar-like structures creating opposed depletion regions which modulate channel current. The gate voltage simultaneously biases the island to enhance the gate electric field effect by removing minority charge carriers which would otherwise accumulate in the bar-like structures.

Recessed-gate junction-MOS field effect transistor

A vertical j-MOSFET useful as a power transistor includes a two-dimensional array of square cells in which a small fraction of the cells are replaced by a double-junction sink useful for collecting the minority carriers in the channel regions that normally will accumulate at each interface of the gate electrode and channel region.

Vertical depletion-mode j-MOSFET

A method is provided for selectively etching ion-implanted silicon dioxide. A masked silicon dioxide layer is exposed to an ion beam of controlled dose and energy. The mask is removed and the silicon dioxide layer is brought in contact with an aqueous ammoniacal hydrogen peroxide solution which preferentially removes the ion-bombarded region with minimal etching of the unimplanted silicon dioxide.

Method for patterning silicon dioxide with high resolution in three

A bearing element having an adherent score-resistant coating on its surface comprising a carbonized layer of an organic resin in which the layer is carbonized by ion implantation. The ion implantation is controlled to not only provide graphite-like and diamond-like structures in the carbonized coating but to also produce chemical bonding between carbon atoms of the resultant coating and atoms of the bearing surface.

Method of making adherent score-resistant coating for metals

A thin film insulated gate field effect transistor having an opposite conductivity type island in its channel region. The island is electrically shorted to the transistor gate electrode.

Junction-MOS power field effect transistor

Metal bearing surface having an adherent score-resistant coating

A hard and adherent coating is formed from a sulfur-free organic resin coating by ion bombardment at an initial range, to at least partially carbonize the coating, and then at a lesser range, to enhance scratch resistance through improved adhesion.

Hard and adherent layers from organic resin coatings

Master and working photomasks are made using a photoresist darkened on and bonded to respective quartz substrates. The working photomask is formed by deep ultraviolet light exposure through an electron beam patterned master mask. Deep ultraviolet light is also used to pattern a resist on a silicon slice through the working mask. The same resist is preferably used on the slice and both masks.

High resolution lithography system for microelectronic fabrication

Low dosage phosphorus implantation regions in &lt;100&gt; P-type silicon are subjected to a severe damage implant with halogen or silicon ions, preferably fluorine and chlorine. This permits anneal in a strongly oxidizing atmosphere for PN junction passivation, without concurrently inducing PN junction leakage. Oxide passivated PN junctions are formed having leakages as low as when the low dose phosphorus implants are annealed in other atmospheres, or are formed in &lt;111&gt; silicon.

Method of low dose phoshorus implantation for oxide passivated diodes in

Boron implantation regions in &lt;100&gt; N-type silicon are subjected to a severe damage implant before anneal in a strongly oxidizing atmosphere that provides a passivating silicon dioxide surface layer. Diodes are formed having leakages as low as when such regions are annealed in other atmospheres or are formed in &lt;111&gt; silicon. In a preferred example, BF.sub.2.sup.+ is used to simultaneously implant boron into a region and convert it to amorphous silicon.

Method of forming diodes by amorphous implantations and concurrent

An improved method of making bipolar monolithic integrated circuits by successive diffusions of boron and phosphorus. Selective halogen ion implantation is used to locally specifically enhance phosphorus diffusion. The halogen implant is performed prior to the boron diffusion. Enhanced local phosphorus diffusion provides selected transistors in the circuit with a narrower base width than others, and a corresponding higher current gain than others. Analogously, higher value pinch resistors can be selectively produced in the circuit.

Growing community of inventors

Lathrup Village, MI, United States of America

Bernard A MacIver