Lexar Media, Inc.

Micron Technology Incorporated

Avalanche Technology, Inc.

Lexar Microsystems, Inc.

Berhanu Iman

Petro Estakhri

Ngon Van Le

Siamack Nemazie

Neal Anthony Galbo

Ali R Ganjuei

Joumana Fahim, Legal Representative

Min Guo

William E Benson

Ravishankar Tadepalli

Michael George

Farshid Tabrizi

Ruchir Shah

Mahmud M Assar

Robert Reid

Robert Alan Reid

The present invention is directed to a computer subsystem that includes a central processing unit (CPU); one or more byte-addressable memory modules having a dual in-line memory module (DIMM) form factor connected to the CPU via a first memory channel; and a master persistent memory module and one or more slave persistent memory modules having the DIMM form factor connected to the CPU via a second memory channel. The master persistent memory module and the one or more slave persistent memory modules are connected in a daisy chain configuration. The one or more slave persistent memory modules receive commands directly from the master persistent memory module.

Serial link storage interface (SLSI) hybrid block storage

The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.

Management of memory array with magnetic random access memory (MRAM)

An image rescue system includes an application program for communication with a mass storage device, the application program being in communication with an operating system layer for accessing the mass storage device to read and write information. The image rescue system further includes a device driver in communication with the application program, the operating system layer and the mass storage device, the device driver for allowing the application program to access the mass storage device to read and write information by bypassing the operating system layer, the device driver for communicating with the mass storage device to allow the application program to access information in the mass storage device considered damaged by the operating system layer, the damaged information being inaccessible to the operating system layer, wherein the image rescue system accesses the mass storage device to retrieve and recover information accessible and inaccessible to the operating system layer.

Image rescue

Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Dynamic memory cache size adjustment in a memory device

Methods of operating a memory, and memories for performing such methods, include determining that a particular area of the memory is defective, locating a free area of the memory, programming data intended for the particular area of the memory to the free area of the memory, checking the particular area of the memory for data previously programmed to the particular area of the memory, and moving any previously-programmed data from the particular area of the memory to the free area of the memory.

Managing defective areas of memory

In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status.

Electronic system having memory with a physical block having a sector storing data and indicating a move status of another sector of the physical block

In an embodiment, a non-volatile memory has erasable blocks of memory cells. The one or more of the erasable blocks include a particular block to be identified by a particular group of logical block addresses corresponding to a predetermined group of sectors.

Memory block identified by group of logical block addresses, storage device with movable sectors, and methods

A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently.

Memory for accessing multiple sectors of information substantially concurrently

Methods of directly accessing a mass storage data device without communicating through an operating system layer are useful in recovering information previously stored in the mass storage device.

Methods of directly accessing a mass storage data device

A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the memory unit are organized into one or more sub-blocks configured to store sectors of information from a host. The sectors of information can be identified by sector numbers of a predetermined order. The memory control circuitry is configured to write a sector of information to a location of a particular sub-block of a particular block. The memory control circuitry is further configured to write a sector of information to a location of a sub-block of the particular block that is other than the particular sub-block, regardless of the predetermined order of the sector numbers of the sectors of information. The memory control circuitry is further configured to write the sectors of information to the locations of the sub-blocks of the particular block substantially concurrently.

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an 'original' location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a 'moved' location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the &#x201c;original&#x201d; physical block address and the &#x201c;moved&#x201d; physical block address and for providing information regarding &#x201c;moved&#x201d; sectors within the block being accessed.

Moving sectors within a block of information in a flash memory mass storage architecture

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Growing community of inventors

Sunyvale, CA, United States of America

Berhanu Iman