Recogni Inc.

Berend Ozceri

Gary S Goldman

Pradeep R Joginipally

Eugene M Feinberg

Shabarivas Abhiram

Martin Stefan Patz

Jian Hui Huang

Ashwin Radhakrishnan

James Michael Bodwin

Kalyana S Venkataraman

Ramalingam K Anand

Chung Y Lau

Jigar K Savla

Michael Davie

Shijun Li

Gilles J C A Backhus

Gilles JCA Backhus

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer/deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and/or memory interface; and a data interconnect communicatively coupling each respective memory element and/or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and/or datagram communication over a cell-based switch fabric to and from the respective memory elements and/or memory interfaces of the plurality of inference engine clusters via the data interconnect.

AI accelerator integrated circuit chip with integrated cell-based fabric adapter

Dynamic data quantization may be applied to minimize the power consumption of a system that implements a convolutional neural network (CNN). Under such a quantization scheme, a quantized representation of a 3×3 array of m-bit activation values may include 9 n-bit mantissa values and one exponent shared between the n-bit mantissa values (n<m); and a quantized representation of a 3×3 kernel with p-bit parameter values may include 9 q-bit mantissa values and one exponent shared between the q-bit mantissa values (q<p). Convolution of the kernel with the activation data may include computing a dot product of the 9 n-bit mantissa values with the 9 q-bit mantissa values, and summing the shared exponents. In a CNN with multiple kernels, multiple computing units (each corresponding to one of the kernels) may receive the quantized representation of the 3×3 array of m-bit activation values from the same quantization-alignment module.

Low power hardware architecture for a convolutional neural network

A three-dimensional model of the environment of one or more camera devices is determined, in which image processing for inferring the model may be performed at the one or more camera devices.

Three-dimensional environment modeling based on a multi-camera convolver system

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Los Gatos, CA, United States of America

Berend Ozceri