Samsung Electronics Co., Ltd.

Beomkyu Shin

Jaeyong Jeong

Sungkyu Park

Kuiyon Mun

Yang Seok Ki

Eun Chu Oh

Kui-Yon Mun

Sangoak Woo

Younggeon Yoo

Wonseb Jeong

Chanho Yoon

Jungmin Seo

Myungjune Jung

Hong Rak Son

Junjin Kong

Jae-Yong Jeong

Dong-Min Shin

Jungho Park

Jiyoup Kim

Sung-Kyu Park

Young-Seok Hong

Insu Kim

A non-volatile memory device is provided. The non-volatile memory device includes: sub-blocks provided on a substrate. The sub-blocks include: a first sub-block connected to a first word line group including a first number of word lines; and a second sub-block connected to a second word line group including a second number of word lines. The first sub-block includes: at least one first memory cell storing M-bit data; and second memory cells each storing N-bit data. The second sub-block includes: at least one third memory cell storing K-bit data; and fourth memory cells each storing L-bit data. M, N, K, and L are positive integers, N is greater than M, and L is greater than K. The first number and the second number are different, and the at least one first memory cell and the at least one third memory cell include different numbers of memory cells.

Non-volatile memory device including sub-blocks having different sizes and storage device

A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

Non-volatile memory device, controller and memory system

A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

Storage device, operation method of storage device, and storage system using the same

The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.

Storage device and operating method of storage controller

A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.

Nonvolatile memory device and memory system including nonvolatile memory device

A memory system includes a memory device including memory cells, and a controller that performs a write operation, a read operation, and a check operation on the memory device. During the check operation, the controller controls the memory device to read check data from target memory cells of the memory cells by using a check level, compares the check data with original data stored in the target memory cells, and determines a reliability of the target memory cells or the check data based on a result of the comparison.

Memory system and operating method of memory system

A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

Memory system including a plurality of controllers

A low-density parity check (LDPC) decoder may include a variable node processing unit and a check node processing unit. The check node processing unit includes memory elements storing a check node value. The memory elements are interconnected through two or more paths, and each of the paths may include a total or partial cyclic permutation of the memory elements to transmit the check node value.

Growing community of inventors

Seongnam-si, South Korea

Beomkyu Shin