Skhynix Inc.

Hynix Semiconductor Inc.

Beom-Yong Kim

Seung-Mi Lee

Yun-Hyuck Ji

Deok-Sin Kil

Kee-Jeung Lee

Woo-Young Park

Wan-Gee Kim

Hee-Young Jeon

Hyung-Dong Lee

Won-Joon Choi

Kwan-Woo Do

Ki-Hong Lee

Hun Wook Lee

Hyo-June Kim

Bong-Seok Jeon

Jong-Chul Lee

Heung-Jae Cho

Young-Wook Lee

Kwon Hong

Yong-Soo Kim

Moon-Sig Joo

Kyung-Woong Park

Jung-Ryul Ahn

Jong-Gi Kim

Ji-Hoon Ahn

Yun Hyuck Ji

Jae-Hyoung Koo

Ki-Jeung Lee

Jun-Yeol Cho

A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

Semiconductor device and method for fabricating the same

A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.

Capacitor with high work function interface layer

A method for fabricating a semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.

A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.

A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Threshold switching device, method for fabricating the same and electronic device including the same

Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer.

Electronic device and method for fabricating the same

A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

Semiconductor device with metal gate and high-k dielectric layer, CMOS integrated circuit, and method for fabricating the same

A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.

Semiconductor device having buried bit line and method for fabricating the same

A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

Semiconductor device and electronic device including the same

Growing community of inventors

Gyeonggi-do, South Korea

Beom-Yong Kim