Magnachip Semiconductor, Inc.

Beom Su Kim

Myung Ho Park

Sun Hwan Kim

Dong Seong Oh

Jae Sik Choi

Si Hyeon Go

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

Wafer-level chip-scale package including power semiconductor and manufacturing method thereof

A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.

Growing community of inventors

Cheongju-si, South Korea

Beom Su Kim