Skhynix Inc.

Beom Seok Hah

Jung Hwan Lee

Ji Hwan Kim

Myung Hoon Cho

Seong Jin Park

Myung Su Kim

Kang Woo Park

Seong Uk Kim

Provided herein are a memory system and a method of programming the same. The memory system may include a memory device including memory cells for storing data and a plurality of latches for storing code values indicating the data. The memory device may be configured to program data into each of the memory cells, store an original code value indicating the data in the plurality of latches, and change the original code value stored in the plurality of latches to an erase code value in response to a verification pass, and a memory controller configured to output, to the memory device, a suspend command for suspending at least the programming in response to detecting a sudden power-off and a recovery command for restoring a code value changed to the erase code value.

Memory system restoring changed data and method of programming the same

In an embodiment, a control circuit may include a command interface, a clock selection signal output circuit, and a clock generating circuit. The command interface may output a selection enable signal in response to a command. The clock selection signal output circuit may output, in response to the selection enable signal, a clock selection signal according to various sub-operations performed in a selected operation. The clock generating circuit may generate main clocks having different periods according the clock selection signal.

Control circuit and memory device having the same

A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the nonvolatile memory device operates in a test mode, and generate control signals which are not provided from an external device, based on a reference signal provided from the external device; and a control logic configured to control an operation for the memory cell according to the generated control signals.

Nonvolatile memory device and operating method thereof

A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address.

Nonvolatile memory device and method of operating the same

A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

Semiconductor memory device and operating method thereof

A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

Growing community of inventors

Seoul, South Korea

Beom Seok Hah