Skhynix Inc.

Beom Rae Jeong

Sung Jin Park

Jung Ae Kim

Systems and methods that relate to memory devices are disclosed. In some implementations, a memory system includes a first data storage device and a second data storage device. Each of the first and second data storage devices includes a plurality of memory blocks, each memory block including a plurality of memory cells each operable to store one or more data bits, and page buffers that cache data to be written to the memory blocks or read from the plurality of memory blocks on a page basis, and a controller including a cache memory configured to temporarily store first data, and configured to move the first data from a portion of the cache memory to one or more of the page buffers of the first data storage device and allocate the portion of the cache memory as a temporary buffer for storing data.

Memory system and operating method thereof

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory cells and a memory controller. The memory controller may be configured to control the memory device to generate dummy data based on write data, when a size of the write data is less than a preset size, and to store program data including the write data and the dummy data in selected memory cells among the plurality of memory cells.

Storage device and method of operating the same

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system writes, when performing the sudden power-off recovery operation, a plurality of target segments which are segments most recently written to each of the plurality of open memory blocks among the plurality of memory blocks to a target memory block among the plurality of memory blocks.

Memory system and operating method of memory system

A memory controller and a method of operating the same may provide recovery from a Sudden Power-Off (SPO). The memory controller may control a memory device including a plurality of memory blocks, each memory block having a plurality of pages. The memory controller may include a dummy program controller configured to, after an SPO has occurred while a program operation was being performed on a page of the memory device, control a dummy program operation for recovering from the SPO; a parity data controller configured to control resetting and generation of parity data for chipkill decoding based on pages on which the dummy program operation is determined to be performed; and a valid data controller configured to control movement of valid data based on a number of pages on which the dummy program operation is to be performed.

Memory controller and method of operating the same

A memory system includes a nonvolatile memory device; and a controller configured to receive an operation command for a target logical address from a host device, and control the nonvolatile memory device in response to the operation command, wherein the controller determines a target logical address range including the target logical address among a plurality of logical address ranges, and determines whether the target logical address has a sequential attribute, based on a target count corresponding to the target logical address range among counts corresponding to the plurality of logical address ranges.

A memory system may include: a nonvolatile memory device including a memory cell array and a page buffer coupled to the memory cell array; and a controller configured to interface with the nonvolatile memory device, wherein the controller moves descriptors on a cache command from a command queue to a cache queue, the cache command being transferred to the nonvolatile memory device, and selectively moves the descriptors moved to the cache queue to a response queue.

A data storage device includes a nonvolatile memory device; and a controller including a plurality of buffers and suitable for, when a program fail occurs in the nonvolatile memory device, transmitting exchange data stored in an optional exchange buffer among the plurality of buffers, to the nonvolatile memory device, storing and updating, in the exchange buffer, failed program data received from the nonvolatile memory device, and transmitting the updated program data to the nonvolatile memory device.

Growing community of inventors

Gyeonggi-do, South Korea

Beom Rae Jeong