Samsung Electronics Co., Ltd.

Beom Kyu Shin

Jun Jin Kong

Hong Rak Son

Heon Hwa Cheong

Dong Min Shin

Se Jin Lim

Yeong Geol Song

Jae Hong Kim

Hyun Jin Choi

Kyoung Lae Cho

Yong June Kim

Myungkyu Lee

Jong Seon No

In-Su Kim

Alain Tran

Myung Kyu Lee

Woo Seong Cheong

Jae Dong Yang

Seok Il Youn

Junjin Kong

Kijun Lee

Dong-Min Shin

Dongmin Shin

Geunyeong Yu

Pil Sang Yoon

Ki Jun Lee

Jiyoup Kim

Kwang Hoon Kim

Sung-Rae Kim

Gyu Yeol Kong

Ung Hwan Kim

Geun Yeong Yu

A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Storage devices with multiple NAND dies

Memory controller, memory device and storage device

A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Method of operating decoder for reducing computational complexity and method of operating data storage device including the decoder

A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.

Data storage system

A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.

Decoder using low-density parity-check code and memory controller including the same

A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality of data chunks.

RAID controller device and storage device configured to recover data having uncorrectable ECC error

An operating method of an error correction decoder includes receiving data, setting initial log-likelihood values of variable nodes, and decoding the received data by updating a log-likelihood value of a selected variable node by use of a minimum value and a minimum candidate value associated with the selected variable node. The minimum value indicates a minimum value of absolute values of log-likelihood values of first variable nodes sharing a check node with the selected variable node and including the selected variable node. The minimum candidate value indicates one from among absolute values of log-likelihood values of second variable nodes that has the smallest value greater than the minimum value. The second variable nodes are selected later than one from among the first variable nodes corresponding to the minimum value.

Storage device including error correction decoder and operating method of error correction decoder

A method of decoding data of a non-volatile memory device is provided. The method includes a first decoding operation of reading first hard decision data from the non-volatile memory device using a first hard decision read level and performing decoding using the first hard decision data; a second decoding operation of reading first soft decision data from the non-volatile memory device when the decoding fails in the first decoding operation, and performing decoding using the first soft decision; and a third decoding operation of changing from the first hard decision read level to a second hard decision read level when the decoding fails in the second decoding operation, reading second hard decision data using the second hard decision read level, and performing decoding either using the second hard decision data or using both the second hard decision data and the first soft decision data.

Data decoding method of non-volatile memory device and apparatus for performing the method

An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.

Iterative decoding method and apparatus

A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.

Hierarchical decoding apparatus

Growing community of inventors

Seongnam-si, South Korea

Beom Kyu Shin