Hynix Semiconductor Inc.

Skhynix Inc.

Beom-Ju Shin

Sang-Sic Yoon

Jee-Yul Kim

Sang-Jin Byeon

Chun-Seok Jeong

Young-Jun Ku

Byung-Il Park

Jeong-Yoon Ahn

A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, and a plurality of memory blocks in which the pages are included; and a controller configured to divide the memory blocks into a first group and a second group, perform a command operation corresponding to a command received from a host, and respectively store segments of user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with type information of the user data Included in the command.

Memory system and operating method of memory system

A data processing system may include: a first memory system including a first memory device, and a first controller of the first memory device; and a second memory system including a second memory device, and a second controller of the second memory device, the first memory system may receive a command from a host, and then checks time information included in the command and performs a first update operation for the first memory device for a first time corresponding to the time information, and the second memory system may perform a second update operation for the second memory device for the first time for which the first update operation is performed.

Data processing system of efficiently processing data in a plurality of memory systems and operating method of controlling data processing system

A memory device includes: a memory including a plurality of blocks, each including a plurality of pages; and a control logic that controls a read operation and a copy-back operation on the memory based on a combination of a block read operation number and a page read operation number.

Memory system having a read and copy-back operation and method for the same

A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command. A pipe latch control unit is configured to control the pipe latch unit to sequentially enable the plurality of pipe latches. An output drive unit is configured to selectively output the internal address or the external address. The internal command is activated after a predetermined latency from an activation timing of the external command.

Internal signal generator for use in semiconductor memory device

A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.

Semiconductor memory device having capability of stable initial operation

Semiconductor device includes a pad for outputting a cyclic redundancy check (CRC) data for error detection and a signal outputting unit for outputting the CRC data or a data strobe signal, which is output together with data of being output in response to a read command, through the pad according to operation modes. Method for operating a semiconductor device provided a step of outputting a CRC data for error detection through a CRC data pad and a step of outputting a data strobe signal, which is output together with data output in response to a read command, through the CRC data pad according to an operation mode.

Semiconductor device and method for operating the same

Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.

Semiconductor memory device for high-speed data input/output

A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

Memory device having latch for charging or discharging data input/output line

A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode.

Semiconductor memory device

An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data input terminals, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A DBI determining unit determines a logic value of each of the data according to the sums and the carries that are transmitted from the full adder and the half adder, thereby outputting a DBI signal.

Apparatus and method of generating DBI signal in semiconductor integrated circuit

A semiconductor device comprises a delay locked loop (DLL) configured to control a phase delay of an internal clock to output first and second DLL clocks; an output enable unit configured to generate rising/falling data output enable signals in response to the second DLL clocks; and an output driver configured to output data in response to one of the first DLL clocks selected by the rising/falling data output enable signals, where a phase of the second DLL clock leads that of the first DLL clock.

Delay locked loop for high speed semiconductor memory device

There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

Data input/output multiplexer of semiconductor device

A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for counting the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a CAS latency.

Semiconductor memory device and method for generating output enable signal

A semiconductor memory device includes a delay locked loop to generate a delay control signal corresponding to a detected phase difference between reference and feedback clock signals, a delay locked loop (DLL) clock signal, and the feedback clock signal. The memory device further includes a delay time measurement device to measure a first degree of delay between the reference and feedback clock signals and output a delay measurement value, and an output enable signal generation device to delay read command information synchronized with an external clock signal by a second degree of delay between the reference and DLL clock signals. The output enable signal generation device generates the read command information as final output enable signal by synchronizing the read command information with the DLL clock signal according to the delay measurement value and column address strobe (CAS) latency information.

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Kyoungki-do, South Korea

Beom-Ju Shin