Zhuhai Access Semiconductor Co., Ltd

Zhuhai Yuexin Semiconductor Limited Liability Company

University of Electronic Science and Technology of China

Nexperia B.v.

Benxia Huang

Lei Feng

Xianming Chen

Wenshi Wang

Yejie Hong

Jindong Feng

Bingsen Xie

Lina Jiang

Gao Huang

Xiaowei Xu

Jian Peng

Minxiong Li

Jiangjiang Zhao

Min Gu

Weiyuan Yang

Jun Gao

Jida Zhang

Wei He

Yuan Li

Yuanming Chen

Juchen Huang

Frank Burmeister

Yujun Zhao

Jinxin Yi

Edward Tena

Shigui Xin

Yanlin Dong

Yongzhi Zeng

An embedded inductance structure includes an insulating layer, an inductance located in the insulating layer, a multi-layer conducting circuit located in the insulating layer and on the upper surface and lower surface of the insulating layer, and a multi-layer conductive copper column layer located in the insulating layer. The inductance and the multi-layer conducting circuit are conductively connected via the multi-layer conductive copper column layer, and the inductance includes a magnet and an inductance coil in direct contact with the magnet, and the inductance coil is composed of a multi-layer conductive coil and a conductive copper column located between adjacent conductive coils. The multi-layer conductive coils are respectively in a ring shape with a notch and are disconnected at the notch, and the positions of the conductive copper columns located on the upper side and lower of each conductive coil are different in the longitudinal direction.

Embedded inductance structure and manufacturing method thereof

An embedded packaging structure according to an embodiment of the present disclosure includes an optical communication device embedded in a substrate, and a blocking wall surrounding the working face opening. The optical communication device may include a working face for emitting light or receiving light. The working face may be revealed by a working face opening from a first surface of the substrate. The blocking wall may extend beyond the first surface in a direction away from the first surface.

Embedded packaging structure and method for manufacturing the same

A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.

Package substrate manufacturing method

A manufacturing method for a substrate embedded with integrated inductor includes: providing a bearing plate; manufacturing a first conduction copper column on the bearing plate; arranging a first dielectric layer on the bearing plate which covers the first conduction copper column; opening the first dielectric layer to form a first opening; filling a magnetic material at the first opening; grinding the first dielectric layer so that surfaces of the first conduction copper column and the magnetic material are flush with a surface of the first dielectric layer; removing the bearing plate, etching a metal layer on the surface of the first dielectric layer to form a package substrate; arranging a first circuit layer and a solder mask layer on an upper surface and a lower surface of the package substrate; and forming a window in the solder mask layer corresponding to the first circuit layer.

Substrate embedded with integrated inductor and manufacturing method thereof

An inductor-integrating embedded support frame according to an embodiment of the present disclosure includes a core dielectric layer, a through-opening penetrating through the core dielectric layer, wherein the through-opening is used for embedding and installing a device, and an inductor, wherein the inductor includes a magnetic core embedded in the core dielectric layer and an inductance coil wound around the magnetic core, wherein at least one conductive copper pillar penetrating through the core dielectric layer is provided at the periphery of the through-opening and the inductor.

Inductor-integrating embedded support frame and substrate, and manufacturing method thereof

Disclosed are a method for manufacturing a support frame structure and a support frame structure. The support frame structure is used for embedded packaging, and includes: a metal plate comprising a support region and an opening region, at least one upper dielectric hole and at least one lower dielectric hole being formed respectively in upper and lower surfaces of the support region, the upper dielectric hole being communicated with the lower dielectric hole; at least one set of metal pillars comprising an upper metal pillar and a lower metal pillar, the upper metal pillar and the lower metal pillar being vertically connected to upper and lower surfaces of the metal plate, respectively; a dielectric layer comprising an upper dielectric layer and a lower dielectric layer, the upper dielectric layer and the lower dielectric layer being correspondingly formed on the upper surface of the metal plate and the upper dielectric hole and on a lower surface of the metal plate and the lower dielectric hole, respectively; and at least one core embedding cavity arranged in the opening region, running through the dielectric layer and the metal plate, and spaced from the upper dielectric hole and the lower dielectric hole by the dielectric layer.

Support frame structure and manufacturing method thereof

A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

Capacitor and inductor embedded structure and manufacturing method therefor, and substrate

A cyclic cooling embedded packaging substrate and a manufacturing method thereof are disclosed. The packaging substrate includes a dielectric material body, a chip, a first metal face, a second metal face and a first trace. The dielectric material body is provided with a packaging cavity, the chip is packaged in the packaging cavity, the first metal face is embedded in the dielectric material body, covers and is connected to a heat dissipation face of the chip. The second metal face is embedded in the dielectric material body, connected to a surface of the first metal face, and is provided with a first cooling channel pattern for forming a cooling channel. The first trace is arranged on a surface of the dielectric material body or embedded therein, and is connected with a corresponding terminal on an active face of the chip through a first conductive structure.

Cyclic cooling embedded packaging substrate and manufacturing method thereof

In a fabrication method for a package structure, a copper foil is provided, electroplating is performed on the copper foil to form a cavity sacrificial post, a dielectric material is laminated to form a dielectric layer, wherein an end face of the cavity sacrificial post is exposed to the dielectric layer, a wiring layer is formed on the dielectric layer, the cavity sacrificial post is removed by etching to form a through cavity, a bonding pad is formed on the wiring layer, a reverse side of a device is mounted on the copper foil in the through cavity, and a terminal of the device is wire-bonded with the bonding pad.

Fabrication method for package structure

A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

Temporary carrier and method for manufacturing coreless substrate thereby

A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.

Conductive substrate and carrier plate wiring structure with filtering function, and manufacturing method of same

A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

Hybrid embedded packaging structure and manufacturing method thereof

A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Multi-device graded embedding package substrate and manufacturing method thereof

Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Embedded chip package and manufacturing method thereof

Disclosed are a heat dissipation-electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate. The heat dissipation-electromagnetic shielding embedded packaging structure includes: a dielectric layer including an upper surface and a lower surface, wherein at least one hollow cavity unit is disposed inside the dielectric layer; an insulating layer disposed in the hollow cavity unit, wherein the hollow cavity unit is partially filled with the insulating layer; an electronic element, wherein one end is embedded in the insulating layer, the other end is exposed in the hollow cavity unit, and the electronic element includes terminals; a through hole penetrating through the upper surface and the lower surface of the dielectric layer and communicating with the terminals; and a metal layer covering the six surfaces of the dielectric layer and the interior of the through hole to form a shielding layer and circuit layer respectively.

Growing community of inventors

Guangdong, China

Benxia Huang