Hewlett-packard Company

Brocade Communications Systems, Inc.

Mcdata Corporation

Bent Stoevhase

Robin Purohit

Robert H Grant

David Book

David C Banks

Paul Ramsay

Steven L Farnworth

Gregory T Sullivan

Kumar Mallavalli

Kumar Malavalli

A modular Fibre Channel switch includes a data switching path and a message switching path to provide logical point to point connections between switch ports. The data switching path includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports. The switch includes a motherboard containing an embedded G_Port ASIC, a message crossbar switch to handle message passing and shared memory that is used to perform data switching. The switch also includes a central processing unit daughter board and external switch port daughter boards.

Fibre channel switching system and method

A modular Fibre Channel switch includes a data switching path and a message switching path to provide logical point to point connections between switch ports. The data switching path includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports. The switch includes a motherboard containing an embedded G.sub.-- Port ASIC, a message crossbar switch to handle message passing and shared memory that is used to perform data switching. The switch also includes a central processing unit daughter board and external switch port daughter boards.

A method and apparatus for configuring a system that includes a plurality of interconnected components that each supports service parameters for communicating with other components in the system. A determination is made as to which components support service parameters that are compatible, and groups of components having compatible service parameters are identified. Adjacent components exchange information frames that identify their service parameters. Each component compares its service parameters with those of its adjacent components to determine whether they are compatible, updating its own service parameters if necessary. Any component that updates its service parameters issues another information frame. Thus, information frames are exchanged until it is determined which components support compatible service parameters, and what service parameters are to be used for communicating among those components. Additionally, a unique address is automatically assigned to every port in the system. Control over the entire range of available addresses is initially granted to a master component, which assigns unique addresses to its own ports, and then relinquishes control over ranges of addresses to other components which each becomes the managers of the addresses over which it is granted control. Each address manager assigns unique addresses to its ports, and if any extra addresses are available, relinquishes control over those extra addresses to another component.

Method and apparatus for assigning port addresses

A method and apparatus for removing a virtual connection between first and second devices in a communication system that includes at least one switch virtually connecting the first and second devices. An error in the virtual connection can be detected in at least one of the first and second devices and the at least one switch, with the detector transmitting a request to remove the virtual connection. The virtual connection then is removed from the communication system in response to the transmission of the request. The request to remove the virtual circuit may be in the form of an information frame transmitted over the virtual connection, with each system component being removed from the virtual circuit upon its processing of the information frame. Additionally, a method and apparatus for operating the virtual connection between the first and second devices. The virtual connection includes a live state in which information frames are transmitted between the first and second devices over the virtual connection at a minimum guaranteed bandwidth. The virtual connection further includes a dormant state wherein information frames are not transmitted over the virtual connection and the bandwidth guaranteed to the connection is made available to other connections in the system.

Method and apparatus for implementing virtual circuits in a fibre

A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler.

High performance path allocation system and method for a fiber optic

A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler. Significantly, the arbitrator is equipped with fairness insurance mechanisms for insuring that transfer requests are always timely and efficiently serviced.

High performance path allocation system and method with fairness

A system for facilitating data communications in a fiber channel network is presented. The system comprises a fiber optic switch element which enables implementation of a Fiber Channel network by permitting selective interconnection of a plurality of fiber optic channels. The fiber optic switch element permits both circuit and frame switching. The switch element comprises a switch module which is connected to at least one fabric-port within the fiber channel fabric. The switch module allocates switching bandwidth. A path allocation system, which is connected to the switch module, generally directs frames of data between the at least one fabric-port to other fabric-ports located within the fabric. A channel module comprising a port intelligence mechanism is disposed between the switch module and the fabric-ports. An element controller provides centralized fabric management.

Switch element for fiber channel networks

A fiber optic switch interconnects ports (p1-pi) for connection with respective fiber optic channels so that a fiber optic network is realized. Channel modules provide the ports. Each channel module has a port intelligence mechanism for each port and a memory interface system for temporarily storing data passing to and from the ports. A switch module having a main distribution network, an intermix distribution network, and a control distribution network interconnects the memory interface systems and permits exchange of data among the ports and memory interface systems. A path allocation system controls the switch module and allocates the data paths therethrough. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the ports. The destination queues are implemented with a double link list in a single memory configuration so that a separate queue structure in hardware is not necessary. Moreover, the scheduler is implemented with a digital signal processor (DSP) with on-chip memory so that the queues are implemented within the on-chip memory and can be accessed at high speed.

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Bent Stoevhase