Motorola Corporation

Benson Chau

David P Gurney

Vipul Anil Desai

Anthony R Schooler

Yun H Kim

Zhuan Ye

William John Rinderknecht

A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a first plurality of cross connections to the second vector arithmetic logic unit; wherein the second register file as a second plurality of cross connections to the first vector arithmetic logic unit.

Method and apparatus for vector processing

The invention provides a method for generating a code sequence. A code-generation instruction is received from memory. One or more control signals are determined based on the code-generation instruction. A code sequence is generated based on the control signals, a current state input, and a mask input.

Method and system for a programmable code generator

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Mt. Prospect, IL, United States of America

Benson Chau