Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies

Benoit Mathieu

Claire Fenouillet-Beranger

Olivier Gillia

Come-Emmanuel Leys

Philippe Coronel

Shay Reboh

Yves Morand

Fabrice Nemouchi

Emmanuel Augendre

Perrine Batude

Sylvain Maitrejean

Jean-Charles Barbe

Guy Feuillet

Jesus Zuniga Perez

Frédéric-Xavier Gaillard

Blandine Alloing

Marion Chandesris

Virginie Brandli

Nicolas Mariage

Côme-Emmanuel Leys

A process for obtaining a nitride (N) layer preferably obtained from at least one of gallium (Ga), indium (In) and aluminium (Al), may include: on a stack including a substrate and at least the following layers successively disposed from the substrate: a creep layer having a glass transition temperature, T, and a crystalline layer, forming pads by etching the stack so that each pad includes at least a creep segment formed by at least a portion of the creep layer, and a crystalline segment formed by the crystalline layer; and growing by epitaxy a crystallite on each of the pads and continuing the epitaxial growth of the crystallites so as to form the nitride layer. The epitaxial growth may be carried out at a temperature T, such that T≥k1×T, with k1 being 0.8.

Process for obtaining a nitride layer

A bench for mechanical characterisation of a battery cell by applying a compression force includes a frame having a first compression plate, a movable element having a second compression plate opposite the first compression plate, a compression spring for applying a compression force to the cell between the first and second compression plates, a force sensor inserted between the movable element and the spring, and movement sensors measuring the movement between the first and second compression plates. The first compression plate includes a projecting compression zone with an area equal to a portion of interest of the cell and the frame includes a recess surrounding a thicker frame in the frame forming a pedestal supporting the first compression plate.

Bench for mechanical characterisation of thin objects

A bench for mechanically characterising a battery cell by applying a compressive force includes a frame carrying a bottom compression assembly and a top compression assembly, means for applying a compressive force to the cell between the compression assemblies, and a force sensor. Each compression assembly includes a compression part and a mounting surrounding the compression part. The compression part and the mounting are at least partly mechanically dissociated. The mounting of the top compression assembly carries movement sensors that measure the movement between the two mountings.

Bench for mechanically characterising thin objects with increased reliability

Method for producing a device provided with FinFET transistors, comprising the following steps:

Method for manufacturing pairs of CMOS transistors of the 'fin-FET' type at low temperatures

A method of straining a transistor channel zone is provided, including a) forming a plurality of stress blocks based on a material having an intrinsic stress, around a zone based on a semiconducting material in which a transistor channel will be made and on which a transistor gate will be formed, the stress blocks inducing a stress in the zone; b) forming a gate block on the zone, the gate block being disposed between the stress blocks; and c) at least partially removing the stress blocks without removing the gate block, wherein the gate block has a Young's modulus and a thickness such that the stress blocks are at least partially removed in step c) and the induced stress is at least partially maintained in the zone after the stress blocks are at least partially removed.

Enhanced method of stressing a transistor channel zone

Method for fabricating transistors for an integrated 3D circuit, comprising:

Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit

This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b) providing a second structure successively including a substrate, an active layer, an intermediate layer, a first semiconducting layer and a porous second semiconducting layer; c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer; d) removing the substrate of the second structure so as to expose the active layer; e) adding dopants to the first semiconducting layer or to the active layer; f) irradiating the first semiconducting layer by a pulse laser so as to thermally activate the corresponding dopants.

Fabrication method of a stack of electronic devices

A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.

Method of modifying the strain state of a semiconducting structure with stacked transistor channels

This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer; a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device; b) bombarding the polycrystalline semiconductor layer by a beam of species configured to form an amorphous part and to preserve a superficial polycrystalline part; c) bonding the first and second structures; d) removing the second substrate of the second structure; e) introducing dopants into the amorphous part, through the exposed active layer; f) thermally activating the dopants by recrystallization of the amorphous part.

Growing community of inventors

Grenoble, France

Benoit Mathieu