Kalray

Benoit Dupont De Dinechin

Michel Harrand

Vincent Ray

Nicolas Brunie

Marta Rybczynska

Alexandre Blampey

Yves Durand

Thomas Champseix

Pierre Guironnet De Massas

Julien Le Maire

Duco Van Amstel

Florent Dupont De Dinechin

Arnaud Odinot

The disclosure relates to an interprocessor synchronization system, comprising a plurality of processors; a plurality of unidirectional notification lines connecting the processors in a chain; in each processor: a synchronization register having bits respectively associated with the notification lines, connected to record the respective states of upstream notification lines, propagated by an upstream processor, and a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor.

Configurable inter-processor synchronization system

A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.

Processor with a configurable distribution of privileged resources and exceptions between protection rings

A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.

Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references

The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.

Blockwise matrix multiplication system

The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

Atomic instruction having a local scope limited to an intermediate cache level

A token bucket flow rate limiter is provided for a data transmission, comprising a token counter configured to be incremented at a rate determining the average flow rate of the transmission; a frequency divider connected to control incrementing of the token counter from a clock, the divider having an integer division factor; and a modulator configured to alternate the division factor between two different integers so as to make the resulting average flow rate tend to a programmed flow rate comprised between two boundary flow rates respectively corresponding to the two integers.

Token bucket flow-rate limiter

A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q&#x3e;2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.

Growing community of inventors

Grenoble, France

Benoit Dupont De Dinechin