Arteris, Inc.

Benoit De Lescure

Moez Cherif

John D Coddington

Syed Ijlal Ali Shah

Alexis Boutiller

Jean Philippe Loison

Sanjay Despande

Michael G Frank

Parimal Gaikwad

Xavier Van Ruymbeke

Mohammed Khaleeluddin

Rohit Bansal

Jean-Philippe Loison

Mokhtar Hirech

Vincent Thibaut

K Charles Janac

Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.

System and method for deadlock detection in network-on-chip (NoC) having external dependencies

A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.

System and method for transaction broadcast in a network on chip

System and methods are disclosed for aggregating identical requests sent to a target from multiple initiators through a network-on-chip (NoC). The requests are marked for aggregation. The NoC uses request aggregators (RA) as an aggregation point to aggregate the identical requests that are marked for aggregation. At the aggregation point, the identical requests are reduced to a single request. The single request is sent to the target. The process is repeated in a cascaded fashion through the NoC, possibly involving multiple request aggregators. When a response transaction is received back from the target, which is at the aggregation point closest to the target, the response transaction is duplicated and sent to every original requester, either directly or through other request aggregators, which further duplicate the already duplicated response transaction.

System and method for performing transaction aggregation in a network-on-chip (NoC)

An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.

Incremental topology modification of a network-on-chip

In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).

System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)

Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.

Topology synthesis of a network-on-chip (NoC)

Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.

System and method for editing a network-on-chip (NOC)

A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

Constraints and objectives used in synthesis of a network-on-chip (NoC)

Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.

Automatic configuration of pipeline modules in an electronics system

Broadcast adapters in a network-on-chip

A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.

Switch with virtual channels for soft locking in a network-on-chip (NoC)

Qualifying networks properties that can be used for topology generation of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metrics are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to determine if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wire length used by the network.

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Campbell, CA, United States of America

Benoit De Lescure